Abstract
In this work, we report on the significance of non-overlap channel architecture in nanoscale double gate (DG) FETs to improve performance of low-voltage analog and digital circuits. It is shown that the low-voltage operation of a cascoded Operational Transconductance Amplifier (OTA) and 6-T SRAM cell can be considerably enhanced using underlap gate-source/drain design. The present work provides new opportunities for realizing future low-voltage analog and digital circuits with underlap DG FETs.
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