Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

Abstract

In this work, we report on the significance of gate–source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (AVO_OTA) > 55 dB and unity gain frequency (fT_OTA) ∼ 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in AVO_OTA and three fold enhancement in fT_OTA over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. AVO_OTA values exhibited by a DG MOSFET-based OTA are 1.3–1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. fT_OTA values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in AVO_OTA and fT_OTA highlights the usefulness of underlap channel architecture in improving gain–bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve ‘idealized’ DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 µA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.