Abstract
This paper presents the design insights and performance benchmarking of Tunnel FET (TFET) based low voltage digital and analog circuits to enable self-powered (energy harvesting based) wearable SOCs for vital sign monitoring etc. This work addresses some important challenges faced by nano scale CMOS digital and analog circuit designers at low voltages. This work demonstrates how TFET's device level chracteristics (steep subthreshold slope, large I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> etc,) translate into favourable circuit performance metrics (power, delay and energy consumption etc, for digital and gain, g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , BW, GBW, FoM etc, for analog). TFETs are promising for designing robust, reliable and energy efficient circuits with supply voltage scaling for ultra-low power applications. The performance of TFET circuits is benchmarked with 20nm FinFET technology as base line comparison.
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