Underlap Channel Research Articles

Investigation and optimization of electro-thermal performance of Double Gate-All-Around MOSFET

The Double Gate-All-Around (DGAA) MOSFET and GAA NWFET are compared and analyzed from both electrical and thermal perspectives under four different conditions by adjusting the channel radius of the NWFET (RGAA). DGAA MOSFET is found to easier form volume inversion than GAA NWFET, and has the advantage of better gate controllability and drivability and the primary concern of worse heat dissipation efficiency. Hetero-Gate-Dielectric (HGD) structure, channel design and spacer engineering are adopted to weaken the serious SHEs in DGAA MOSFET while maintaining a good SCEs immunity. Results show that the DGAA MOSFET with the single-k Al2O3 spacer can generate a better trade-off between electrical and thermal performance than other spacer combinations. In addition, the improvement in thermal performance of DGAA MOSFET by the HGD structure is relatively limited. Compared with GAA NWFET without stacking, the optimized DGAA MOSFET with single-k Al2O3 spacer, appropriate channel thickness (Tch = 5 nm) to form volume inversion and underlap channel (Lun = 4 nm) has better electrical characteristics whose drivability improves at least twice with similar Rth.

Enhanced logic gates and SRAM based on reconfigurable field-effect transistor with asymmetric spacer engineering

In this paper, an early evaluation of reconfigurable field-effect transistor (RFET) with asymmetric spacer engineering in terms of logic cells and static random-access memory (SRAM) is carried out using 3D-TCAD and logical effort theory. The asymmetric underlap channel extension at the drain side (UCED) is demonstrated to be able to increase the on-state saturated current (I ON). Furthermore, the proposed UCED RFET shows great stability for different spacer materials, compared to the conventional RFET. Though a slight deterioration of the normalized delay in UCED RFET, the propagation delay of UCED structure is still smaller due to the lower intrinsic delay in the transistor level because control gate capacitance reduces in the meantime. RFET with asymmetric spacer engineering is also demonstrated to relax the competition between the read and the write operation in SRAM.

Novel Reconfigurable Field-Effect Transistor With Asymmetric Spacer Engineering at Drain Side

In this article, a novel reconfigurable field-effect transistor with an asymmetric underlap channel extension at drain side (UCED-RFET) is proposed for the first time. The influence of underlap extension is investigated by extensive 3-D device simulation. Results show that compared to the conventional RFET with symmetrical underlap-channel extension at source and drain end, the ON-state saturated current ( ${I}_{ \mathrm{ON}}$ ) of our proposed UCED-RFET is greatly increased without degenerating the OFF-state leakage current ( ${I}_{ \mathrm{OFF}}$ ), and the ratio of ${I}_{ \mathrm{ON}}/{I}_{ \mathrm{OFF}}$ is up to 109. The underlying physical mechanism is explored and the enhanced gate coupling is demonstrated to contribute to the improved performance in our proposed UCED-RFET. Moreover, the effects of gate dielectric materials and different spacers are investigated, and the results correlated with the scaling properties are also reported.

Impact of positions of sensing area in ahannel of dielectric modulated MOSFET based biosensor

In this work, a gate underlap channel dielectric-modulated (DM) double-gate (DG) MOSFET which is working as biosensor for the label free electrical detection of the biomolecules has been investigated. The electrical characteristics such as, threshold voltage and drain current of DM DG MOSFET have been studied by the device simulation. The shift in the threshold voltage has been used as the sensing metric to detect the sensitivity after the biomolecules interacts with the device. four-gate NMOS inverter has also been used to investigate a label free electrical detection of the biomolecules. The work has been done under the consideration of dry environment condition.

Suppression of ambipolar conduction and investigation of RF performance characteristics of gate‐drain underlap SiGe Schottky barrier field effect transistor

In this work, a hetero structure gate-drain underlap (UL) Schottky barrier (SB) Field Effect Transistor (FET) is explored to achieve high device performance compared with high-k and low-k hetero structure SB FET (HSBFET). The effects of gate drain UL junction on the performances of UL-HSBFETs have been studied in terms of electrical characteristics including on-current (Ion), subthreshold swing, Ion/Ioff ratio, ambipolar conduction, and Ioff current. The low on-state current of silicon-based SB FETs can be enhanced by introducing the low bandgap silicon germanium material. Gate-drain UL and silicon germanium channel with low barrier height provides less tunnelling width which enhances the carrier injection at on-state compared with low-k and high-k HSBFET. Further, the proposed UL-HSBFET suppresses the ambipolar conduction due to holes. In contrast to conventional high-k and low-k HSBFET that suffers from severe ambipolar conduction, the UL-HSBFET device reduces the conduction at drain-channel junction with increasing the UL length to 5, 10, 15, and 20 nm. This provides better radio frequency performances with improved carrier capability of the proposed device. Therefore, UL-HSBFET device can be one of the best possible competitor for high-frequency application. The performance comparison of all the devices is carried out using Technology Computer-Aided Design (TCAD) simulator.

Comparison of dual-k spacer and single-k spacer for single NWFET and 3-stack NWFET

The investigation of the Dual-k spacer through comparative analysis of single nanowire-FET(NWFET)/3-stack NWFET and underlap/overlap channel is conducted. It is known that the dug 3-stack NWFET has better delay characteristics than single NWFET with the use of high permittivity material of Cin in Dual-k spacer structure. In addition, there is no difference of delay between overlap and underlap channel when it used Dual-k spacer structure but underlap channel of Dual-k 3-stack NWFET shows better short channel immunity.

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.

Design of Triple Gate for Sub threshold Low Power applications

<p>A novel design of triple gate MOSFET structure with metal gate and an underlap channel is proposed to minimise the short channel and corner effects. The gate metal used is titanium nitride as well as source and drain is diffused with titanium nitride so as to increase the drive capability of the device. To obtain subthreshold threshold voltage operation of the device, the gates are kept symmetric and the gate electrodes corner segments are rounded off to minimise leakage. The device shows significant improvement over conventional double gate FinFET and triple gate device without gate corner round off device in terms of Ion, Ioff ratio, DIBL, subthreshold slope, rise time, fall time.</p>

Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications

We propose herein the underlap channel silicon-on-insulator (SOI) quantum dot (QD) floating-gate (und-SOIQDFG) metal---oxide---semiconductor field-effect transistor (MOSFET). It is found that, although the reduced effective gate voltage due to the voltage drop across the underlap lengths reduces the on-state drive current ($$I_\mathrm{ON}$$ION), the increased effective channel length due to the underlap at the gate---source/drain reduces not only the short-channel effects, gate-induced drain leakage, and off-state leakage current ($$I_\mathrm{OFF}$$IOFF) but also the parasitic overlap capacitances of the proposed und-SOIQDFG device. Furthermore, in comparison with the conventional QD floating-gate (conv-QDFG) MOSFET, the capacitive coupling ratio and memory window of the proposed device are improved by $${\sim }5$$~5 and $${\sim }25$$~25 %, respectively. Furthermore, the $$I_\mathrm{ON}/I_\mathrm{OFF}$$ION/IOFF ratio for the proposed device is improved while the static power dissipation is significantly reduced compared with the conv-QDFG device. This clearly shows that use of the gate---source/drain underlap in the quantum dot floating-gate MOSFET not only eliminates potential weaknesses of the device but also makes it suitable for low-power nanoscale flash memory applications.

Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

Drain Current Model of a Four-Gate Dielectric Modulated MOSFET for Application as a Biosensor

In this paper, an analytical model of a four-gate dielectric modulated MOSFET for label-free electrical detection of the biomolecules has been proposed. To provide a binding site for the biomolecules, the channel region of MOSFET is left open in the four-gate configuration, which is conventionally covered by the gate electrode. As a result, the electrical characteristics of the device are affected by the neutral and charged biomolecules that binds to the underlap (open) channel region. The electrostatics is developed by solving a 2-D Poisson’s equation, assuming a parabolic potential profile along the channel direction using the conformal mapping technique and subsequently the drain current model is developed. The change in the threshold voltage is used as a sensing metric for the detection of biomolecules after their immobilization in the open region. The characteristic trends are supported and verified using the ATLAS device simulation software.

Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits

In this paper, asymmetric drain (ASD) underlap channel dopant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed to improve the scalability and high-frequency performance of DSSB SOI MOSFET. The asymmetry of this device lies in the spacer thickness at the drain which creates an underlap channel with the same dopant-segregation length as that of the overlap channel at the source. The presence of overlap at the source and underlap at the drain of this device not only makes it immune to short-channel effects and the gate-induced drain leakage but also improves the analog figures of merit such as transconductance, intrinsic gain and unity-gain frequency of the device. In addition to this, the inverter power dissipation and the ring-oscillator delay in an optimized ASD underlap device are reduced by ∼40% and ∼20%, respectively, over the symmetric source/drain overlap and underlap channel devices. Thus, the significant improvement in both digital and analog figures of merit at nanoscale shows the suitability of the proposed device for low-power mixed-signal circuits. The proposed fabrication flow of this novel device is also similar to the DSSB SOI MOSFET flow and demonstrates the use of conventional CMOS processes.

Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits

In this paper, it has been shown that employing an underlap channel created by using the dual spacers in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only reduces the off-state leakage, short-channel effects and the parasitic overlap capacitances but also suppresses the variability induced by process fluctuations in the Schottky barrier height, dopant-segregation length and SOI film thickness of the device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off, a novel dual-k spacer underlap channel DSSB SOI structure has also been proposed in which the increased fringing electric field effect due to high-k inner spacer layer not only improves the on-state drive current but also reduces the off-state leakage current in both n-channel and p-channel devices. Despite the presence of high-k inner spacer layer increasing the fringing gate capacitance, the scalability in an optimized dual-k spacer underlap structure has improved by ∼60% and ∼35%, respectively over the conventional spacer overlap and underlap channel structures. In addition, the variability in an optimized dual-k spacer underlap structure has also been reduced by ∼50% and ∼30% respectively over the conventional spacer overlap and underlap channel structures. This clearly indicates that the proposed dual-k spacer underlap structure is a better choice for low-variability nanoscale CMOS logic circuits. The detailed fabrication flow of this novel device has also been proposed which demonstrates the use of conventional CMOS processes.

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at ID=5μA/μm and VDS=0.5V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at VDD=0.5V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ∼20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at VDD=0.5V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ∼10%, ∼35% and ∼25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.

Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain (AVO_OTA) along with three times higher cutoff frequency (fT_OTA) as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle (s/ σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 μA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology.

An underlap field-effect transistor for electrical detection of influenza

An underlap channel-embedded field-effect transistor (FET) is proposed for label-free biomolecule detection. Specifically, silica binding protein fused with avian influenza (AI) surface antigen and avian influenza antibody (anti-AI) were designed as a receptor molecule and a target material, respectively. The drain current was significantly decreased after the binding of negatively charged anti-AI on the underlap channel. A set of control experiments supports that only the biomolecules on the underlap channel effectively modulate the drain current. With the merits of a simple fabrication process, complementary metal-oxide-semiconductor compatibility, and enhanced sensitivity, the underlap FET could be a promising candidate for a chip-based biosensor.

Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate–source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (AVO_OTA) > 55 dB and unity gain frequency (fT_OTA) ∼ 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in AVO_OTA and three fold enhancement in fT_OTA over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. AVO_OTA values exhibited by a DG MOSFET-based OTA are 1.3–1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. fT_OTA values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in AVO_OTA and fT_OTA highlights the usefulness of underlap channel architecture in improving gain–bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve ‘idealized’ DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 µA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon?on?Insulator (SOI) and Germanium?on?Insulator (GOI) MOSFETs. A design methodology, by evaluating the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non?overlapped gate?source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.