Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

Abstract

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at ID=5μA/μm and VDS=0.5V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at VDD=0.5V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ∼20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at VDD=0.5V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ∼10%, ∼35% and ∼25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.