Underfill Process Research Articles

Experimental Characterization of Monotonic and Fatigue Delamination of Novel Underfill Materials

No-flow underfill materials reduce assembly processing steps and can potentially be used in fine-pitch flip chip on organic board assemblies. Such no-flow underfills, when filled with nano-scale fillers, can significantly enhance the solder bump reliability, if the underfills do not prematurely delaminate or crack. Therefore, it is necessary to understand the risk of underfill delamination during assembly and during further thermal excursions. In this paper, the interface between silicon nitride (SiN) passivation and a nano-filled underfill (NFU) material is characterized under monotonic as well as thermo-mechanical fatigue loading, and fracture parameters have been obtained from such experimental characterization. The passivation-underfill interfacial delamination propagation under monotonic loading has been studied through a fixtureless residual stress induced decohesion (RSID) test. The propagation of interfacial delamination under thermo-mechanical fatigue loading has been studied using sandwiched assemblies and a model for delamination propagation has been developed. The characterization results obtained from this work can be used to assess the delamination propagation in flip-chip assemblies. Though the methods presented in this paper have been applied to nano-filled, no-flow underfill materials, their application is not limited to such materials or material interfaces.

Flow Visualization of Solder Ball Arrangement for Underfill Encapsulation of Flip Chip

The flip chip package has the advantages of low cost, low interface, and small volume in IC package. This study describes the analysis of underfill encapsulation between solder balls and microchip by experiment and 3D numerical simulation. The numerical simulation of underfill encapsulation is based on the concept of the control volume finite element method. The parameters of injection situation are used for central point, one line, L-line, and U-line injection types. The different processing parameters (solder ball arrangement, injection pressure, solder ball size, and injection situation) are used for underfill encapsulation. The results show that the free surface shape of the experiment is closer to that of the 3D numerical simulation on the plane flow situation for underfill encapsulation. The injection situation of L-line is the best underfill encapsulation of flip chip irrespective of the different arrangement of solder ball and size of the solder ball. The flow time has the biggest value for the different size of solder ball on an alternate arrangement of the solder ball. The flow time decreases as injection pressure increases. The free surface on the thickness direction is concave for the underfill process of the experiment. The contact angle of the free surface is the same for different injection pressures in underfill encapsulation. This situation indicates that the capillary effect dominates the flow situation in the underfill process.

Sea-of-Leads MEMS I/O Interconnects for Low-k IC Packaging

Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.

Editorial

This special issue on the ‘Characteristic-Based Split (CBS)’ scheme was conceived from the experience of different people working in different areas of computational mechanics. The objective in the main is the presentation of the CBS scheme in its very general form to accommodate general engineering problems of interest to the engineering community. Thus, we have included papers on general fluid dynamics, shallow-water flows, solid dynamics, porous media and heat transfer. A total of eight papers have been included into this special issue. The first paper by Nithiarasu et al. describes the CBS scheme in detail with an explanation on the origin of the characteristic-based procedures and their extension to solve compressible and incompressible flows. This paper also describes the merger of the characteristic-based procedure with a fractional step algorithm to develop the CBS procedure. Several examples are also presented to demonstrate the robustness and accuracy of this unified approach to compressible and incompressible flows. Though only fluid dynamics examples are presented in the first paper, the suitability of the method to solve solid dynamic problems is demonstrated in the second paper by Rojek et al. This paper again demonstrates the novelty of the proposed approach. The presented idea immediately forms the basis for coupled fluid-solid problems using a single approach with different constitutive equations. The third paper is presented by Ortiz et al. which describe the CBS approach to shallow-water problems. Once again the versatility of the method is demonstrated for an entirely different kind of incompressible flow equations. The shallow-water equations presented in this paper resembles the inviscid compressible flows. Thus, it is obvious that the same methodology used to solve the compressible flows can be extended to the shallow-water equations. The next paper is a recent work on porous media problems using the CBS approach. The authors, Salomoni and Schrefler, have demonstrated the use of the CBS scheme to a complicated porous medium problem. Once again this proves that the application of the CBS scheme is not limited to fluid dynamics problems. The next three papers by Massarotti et al., Morandi Cecchi and Venturin and Kulkarni et al. are the applications of the CBS scheme to different engineering problems. In Massarotti et al., the method has been extensively used to steady and unsteady incompressible flows with heat transfer to make a general assessment of the method in its fully explicit and semi-implicit forms. This paper gives an in-depth comparison between the two variations. In Morandi Cecchi and Venturin, the method is applied to solve a practical shallow-water problem of the Venice Lagoon. The third paper in the application series by Kulkarni et al. deals with a practical application of under-fill simulation process in electronic packaging. All these three papers clearly demonstrate the flexibility of the CBS method for different applications of practical importance. This special issue is concluded by a paper on a comparative study between the CBS scheme and other recent methods. This last paper is presented by Codina et al. and compares the CBS method against the family of recent subgrid scale (SGS) methods. Finally, we would like to thank Prof. O. C. Zienkiewicz for supporting this special issue and writing a foreword. We are also grateful to Professor R. W. Lewis, editor of the International Journal for Numerical Methods in Engineering for permitting us to produce this special issue. We hope this special issue will be of great use to the readers to learn about the CBS scheme and its development over the last 10 years.

Numerical simulation of underfill encapsulation process based on characteritsic split method

AbstractElectronic packaging protects the integrated circuit chip from environmental and mechanical damages. Underfilling encapsulation is an electronic packaging technology used to reinforce the solder joints between chip and the substrate. For better mould design and optimization of the process, flow analysis during the encapsulation process is the first necessary step. This paper focuses on the study of fluid flow in underfilling encapsulation process as used in electronics industry. A two‐dimensional numerical model was developed to simulate the mould filling behaviour in underfilling encapsulation process. The analysis was carried out by writing down the conservation equations for mass, momentum and energy for a two‐dimensional flow in an underfilling area. The governing equations are solved using characteristic based split (CBS) method in conjunction with finite element method to get the velocity and pressure fields. The velocity field was used in pseudo‐concentration approach to track the flow front. Pseudo‐concentration is based on the volume of fluid (VOF) technique and was used to track fluid front for each time step.A particular value of the pseudo‐concentration variable was chosen to represent the free fluid surface which demarcates mould compound region and air region. Simulation has been carried out for a particular geometry of a flip‐chip package. The results obtained are in good agreement with the available numerical and experimental values and thus demonstrate the application of the present numerical model for practical underfilling encapsulation simulations. Copyright © 2006 John Wiley & Sons, Ltd.

Study on flow visualization of flip chip encapsulation process for numerical simulation

Flip chip package is the most important technology in IC package necessary for scale, velocity and cost by the development of semiconductor technology and the innovation of computer product. It has the advantages of low cost, low interface and small volume in IC package. This paper emphasizes the analysis for underfill encapsulation between the solder ball and chip. The finite element simulation in a three-dimensional inertia-free, incompressible flow is presented. A control volume scheme with a fixed finite element mesh is employed to predict fluid front advancement. The epoxy is used for the underfill material. The injection situation is used for central point, one line, L line and U line injection. The underfill process is used for different parameters (mold temperature, melt temperature, injection pressure, injection time and injection situation). The results show that the injection situation is the most important factor for processing parameters. The result indicates that the L line injection is the best injection situation for underfill encapsulation of flip chip.

Design and fabrication of a flip-chip-on-chip 3-D packaging structure with a through-silicon via for underfill dispensing

This paper presents a new package design for multichip modules. The developed package has a flip-chip-on-chip structure. Four chips [simulating dynamic random access memory (DRAM) chips for demonstration purpose] are assembled on a silicon chip carrier with eutectic solder joints. The I/Os of the four chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. A through-silicon via (TSV) hole is made at the center of the silicon chip carrier for optional underfill dispensing. The whole multichip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly and X-ray inspection, the underfill process is applied to some selected specimens for comparative study purpose. The underfill material is dispensed through the center TSV hole on the silicon chip carrier to encapsulate the solder joints and the four smaller chips. Subsequently, scanning acoustic microscopy (SAM) is performed to inspect the quality of underfill. After the board-level assembly, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of all specimens is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1200 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, instead of solder joints. The features and merits of the present package design are discussed in details in this paper.

Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60–70μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.

Prediction of mechanical stresses induced by flip-chip underfill encapsulants during cure

A constitutive model is presented for predicting the stresses in thermosetting resins during and after cure. An overview is given of the experimental techniques used for estimating the parameters in this model. The model is validated by comparing its predictions to a second set of measurements that has not been used for the actual parameter estimation. This validation shows that the model is capable of giving fair predictions of the measured stresses. The model is implemented in a commercially available finite element package and its use is demonstrated by applying it to the study of a flip-chip underfilling process.

Resin flow characteristics of underfill process on flip chip encapsulation

Flip chip package is the most important technology in IC package for the necessary of scale, velocity and cost by the development of semiconductor technology and the innovation of computer product. This paper indicates that the analysis for flow visualization of the solder ball and chip between numerical simulation and experiment. A finite element simulation of moving boundaries in a three-dimensional inertia-free, incompressible flow is presented. The injection situation uses for one line injection, L line injection, U line injection and central point injection location. The injection process uses for different parameters (mold temperature, injection temperature, injection pressure, injection time). The results show that the filling situation for numerical simulation is closer to experiment.

Enhancement of Underfill Capillary Flow in Flip-Chip Packaging by Means of the Inertia Effect

This paper describes how the use of inertia forces induced by the rotation of a working disk may be adopted to increase the fill rate of the flip-chip packaging process and thereby reduce the process cycle time. It is shown how the driving forces resulting from the inertia effect are determined by the Weber number. The constant and varying contact angle models are compared under a specified set of process conditions. The calculated flow behavior results indicate that the relationship between the contact angle, the average fluid velocity, the liquid-air interface position, and the filling time depends upon the Weber number. The constant and varying contact angle models are utilized in the analysis of a new processing method referred to as rotation-enhanced underfill packaging (REUP). The inertia effect induced by the angular motion of the working disk is shown to enhance the flow of the underfill encapsulant and to reduce the time of the underfill process. The present results confirm that the rotation of the working disk leads to an increased underfill capillary flow rate, which is beneficial in reducing the production cycle time of the flip-chip packaging process.

Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.

Novel Reworkable Fluxing Underfill for Board-Level Assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.

Residual stresses in microelectronics induced by thermoset packaging materials during cure

This paper presents a constitutive model for predicting the stresses in thermosetting resins during cure. An overview is given of the experimental techniques used for determining the parameters in this model. The model is validated by comparing its predictions to additional measurements, which have not been used for the actual parameter estimation. This validation showed that the model is capable of giving fair predictions of the measured stresses. The model is implemented in a commercially available finite element package and its use is demonstrated by applying it to the study of a flip-chip underfilling process.

A Model for Underfill Viscous Flow Considering the Resistance Induced by Solder Bumps

During the underfill process, polymers driven by either capillary force or external pressure are filled at a low speed between the chip and substrate. Current methods treated the flow in the chip cavity as a laminar flow between parallel plates, which ignored the resistance induced by the solder bumps or other obstructions. In this study, the filling flow between solder bumps was simulated by a flow through a porous media. By using the superposition of flows through parallel plates and series of rectangular ducts, permeability of the underfill flow was fully characterized by the geometric arrangement of solder bumps and flat chips. The flow resistances caused by adjacent bumps were represented in its permeability. The model proposed in this study could provide a numerical approach to approximate and simulate the undefill process for flip-chip technology. Although the proposed model is applicable for any geometric arrangement of solder bumps, rectangular-array of solder bumps layout was used first for comparison with experimental results of other article. Comparisons of the flow-front shapes and filling time with the experimental data indicated that the flow simulation obtained from the proposed model gave a good prediction for the underfill flow.

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.

Study on B-stage properties of wafer level underfills

The flip-chip on organic substrates has relied on the underfill to enhance the solder joint reliability. The invention of wafer level underfill technology has greatly improved the production efficiency of the flip-chip process. Nevertheless, because of the unique curing characteristics of the wafer level underfill, there is a need for a fundamental understanding of the underfill curing process. In this study, we have explored two underfill formulations and have investigated their curing properties and the gelation behavior. The B-stage feasibility of these two underfills was investigated based on modeling of the curing process and characterization of the material properties. It was found that the epoxy/anhydride formulation was not suitable for wafer level underfill application, due to its low degree of cure at gelation and its low Tg after the B-stage. The underfill formulation based on epoxy/anhydride system was optimized for good dicing property and curing latency in a reflow process. A successful wafer level underfill material and process were demonstrated.

Externally guided underfill encapsulation and subsequent filler particle migration during electronics packaging

We present a numerical study of the transient multiphase flow of a liquid encapsulant in a microgap formed between parallel plates with special reference to electronics packaging. The surface tension and polarization forces are assumed to drive the fluid flow. The governing equations are solved using the volume of fluid model within the framework of the finite volume method in order to predict the free surface front of the encapsulant together with the time and spatial evolution of filler particle concentration during the underfill process. The numerical results are found to be in good agreement with available reported experimental data. The influence of the polarization force is found to reduce the encapsulant fill time, increase the flow length and distribute the filler particles to a larger flow length. The new process has practical implications, such as overcoming the partial curing of underfill epoxy before the flow is complete.

COMPUTER SIMULATION OF FLIP-CHIP UNDERFILL ENCAPSULATION PROCESS USING MESHFREE PARTICLE METHOD

International Journal of Computational Engineering ScienceVol. 04, No. 02, pp. 405-408 (2003) Design, Modelling and SimulationNo AccessCOMPUTER SIMULATION OF FLIP-CHIP UNDERFILL ENCAPSULATION PROCESS USING MESHFREE PARTICLE METHODM. B. LIU, G. R. LIU, and K. Y. LAMM. B. LIUCentre for ACES, Department of Mechanical Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260, Singapore Search for more papers by this author , G. R. LIUCentre for ACES, Department of Mechanical Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260, Singapore Search for more papers by this author , and K. Y. LAMCentre for ACES, Department of Mechanical Engineering, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260, Singapore Search for more papers by this author https://doi.org/10.1142/S1465876303001381Cited by:4 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractThe underfill encapsulation process is very important in the flip-chip technology for advanced IC packaging. This paper presents the application of smoothed particle hydrodynamics (SPH) to simulate the complex underfill encapsulation process. The incompressible flow in the micro channel between the chip and the substrate is modeled as an artificially compressible flow. The simulation result of the underfill encapsulation agrees well with the analytical solution.Keywords:Underfill encapsulationSmoothed particle hydrodynamicsMicro channel flow References S. J. Han and K. K. Wang, Analysis of the flow of encapsulant during underfill encapsulation of flip-chip, IEEE Transactions on components, packaging, and manufacturing technology, past B, 20 (4) (1997):424-433 . Google Scholar Z. H. Gao, H. Xue and G. R. Liu, Computational simulation of flip-chip underfill encapsulation process, Proceedings of the 5th International Symposium on Heat Transfer, (2000), Beijing . Google Scholar R. A. Gingold and J. J. Monaghan, Smoothed Particle Hydrodynamics: Theory and Application to Non-spherical stars, Monthly Notices of the Royal Astronomical Society 181, (1977):375-389 . Google ScholarM. B. Liu, G. R. Liu and K. Y. Lam, Shock Waves 12(3), 181 (2002). Crossref, Google ScholarM. B. Liuet al., Computational Mechanics 30(2), 106 (2003). Crossref, Google ScholarJ. P. Morris, P. J. Fox and Y. Zhu, Journal of Computational Physics 136, 214 (1997). Crossref, Google Scholar FiguresReferencesRelatedDetailsCited By 4Numerical implementation of deformation and motion of droplet at the interface between vapor and solid surface with smoothed particle hydrodynamics methodology Qiang Hong-Fu, Liu Kai and Chen Fu-Zhen1 Jan 2012 | Acta Physica Sinica, Vol. 61, No. 20MODELING OF CONTACT ANGLES AND WETTING EFFECTS WITH PARTICLE METHODSM. B. LIU, J. Z. CHANG, H. T. LIU, and T. X. SU20 November 2011 | International Journal of Computational Methods, Vol. 08, No. 04Smoothed Particle Hydrodynamics (SPH): an Overview and Recent DevelopmentsM. B. Liu and G. R. Liu13 February 2010 | Archives of Computational Methods in Engineering, Vol. 17, No. 1AN OVERVIEW ON SMOOTHED PARTICLE HYDRODYNAMICSM. B. LIU, G. R. LIU, and Z. ZONG20 November 2011 | International Journal of Computational Methods, Vol. 05, No. 01 Recommended Vol. 04, No. 02 Metrics History KeywordsUnderfill encapsulationSmoothed particle hydrodynamicsMicro channel flowPDF download

Double-layer no-flow underfill materials and process

The no-flow underfill has been invented and practiced in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. Chip scale package (CSP) components are assembled using the double-layer no-flow underfill process. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. With a high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation.