Underfill Process Research Articles

Image segmentation on void regional formation in the flip-chip underfilling process by comparing YOLO and mask RCNN

Purpose This paper aims to identify a suitable convolutional neural network (CNN) model to analyse where void(s) are formed in asymmetrical flip-chips with large amounts of the ball-grid array (BGA) during underfilling. Design/methodology/approach A set of void(s)-filled through-scan acoustic microscope (TSAM) images of BGA underfill is collected, labelled and used to train two CNN models (You Look Only Once version 5 (YOLOv5) and Mask RCNN). Otsu's thresholding method is used to calculate the void percentage, and the model's performance in generating the results with its accuracy relative to real-scale images is evaluated. Findings All discoveries were authenticated concerning previous studies on CNN model development to encapsulate the shape of the void detected combined with calculating the percentage. The Mask RCNN is the most suitable model to perform the image segmentation analysis, and it closely matches the void presence in the TSAM image samples up to an accuracy of 94.25% of the entire void region. The model's overall accuracy of RCNN is 96.40%, and it can display the void percentage by 2.65 s on average, faster than the manual checking process by 96.50%. Practical implications The study enabled manufacturers to produce a feasible, automated means to improve their flip-chip underfilling production quality control. Leveraging an optimised CNN model enables an expedited manufacturing process that will reduce lead costs. Originality/value BGA void formation in a flip-chip underfilling process can be captured quantitatively with advanced image segmentation.

Accurate numerical simulations of capillary underfill process for flip-chip packages

Accurate numerical simulations of capillary underfill process for flip-chip packages

Effect of flip-chip ball grid array structure on capillary underfill flow

During the capillary underfill (CUF) process in flip-chip packaging, issues like incomplete filling, voids, wire sweeping, and overflow can impact product reliability and the relatively long filling time required. Therefore, finding ways to improve filling efficiency is a critical challenge. Conducting experiments to address these issues can be costly. As a result, the industry often relies on simulation software to simulate the actual manufacturing process, predict potential problems, compare results with experimental data, and analyze ways to improve the process. This approach helps enhance the package yield and further improves production efficiency.This study investigates the capillary underfill (CUF) process through simulation. Firstly, the viscosity and reaction kinetics of the underfill material are measured to establish the necessary data for the simulation. Then, Moldex3D, a mold flow simulation software, is used to create the model, generate the mesh, and perform the process simulation analysis. The effects of material properties and process parameters on the capillary underfill process are considered. The simulation results are compared with experimental data to validate the feasibility of the simulation. Subsequently, different flip-chip package structures and CUF process parameters are analyzed through simulation to explore the impact of these parameters on the flow pattern and filling efficiency of the adhesive material during the filling process.According to the simulation results, the filling speed is faster when the bump pitch and gap height are larger. However, the required filling time still has a considerable relationship with the volume of the filling region. Dispensing from the side with lower bump density can shorten the filling time when the bump distribution is uneven.

Correlation Study on Voiding in Underfill of Large Quantity Ball Grid Array Chip Using Machine Learning

Abstract This paper investigates voiding issues in the underfilling process of ball grid array (BGA) chip packages under various parameter settings such as chip conveyor speed, valve pressure, temperature, and dispense pattern complicate. The study identifies valve pressure as the primary cause of voiding in large quantity BGA chips, achieving 88.9% in accuracy, supported with the deformation of the valve nozzle. Additionally, the findings reveal that racing effects occurs due to asymmetry of the solder ball array arrangement with percentage difference between the TSAM BGA chips experiments and its simulation counterparts in the range of 0.089–3.65%.

Numerical Analysis of Narrow-gap Underfill Flow in the Flip-chip Process Using the Lattice Boltzmann Method

Flip-chip packaging is a first-level interconnect technology, and to predict its melt front of capillary driven underfill analytical models have been made. Using the Analytical models, prediction of the melt front can be efficiently done, however it is difficult to reflect the flow resistance resulting from complex solder bump arrangement. Therefore, 3D numerical analysis is required. In this study, Lattice Boltzmann method (LBM) is used for observing the micro void generation that occurs in a underfill process with a height of several tens of microns. LBM statistically expresses the motion of the molecule, to solve the mass transfer of the microscale. In particular, LBM has strengths in multiphase flow analysis of several microscales that cannot be solved by continuum assumption. In this paper, underfill process of several tens of micro scales, which was not covered in previous 3D numerical analysis studies, was simulated using LBM. The improvement of the new LBM model, which more accurately simulates the resistance due to pressure by considering collisions between air and molten mold molecules, is introduced. With the hydraulic diameter greatly reduced due to the narrow gap, it is observed how the solder bump pitch affects the micro void generation. And it is observed whether the air ventilation could change significantly according to the ambient pressure.

Deep learning and analytical study of void regional formation in flip-chip underfilling process

PurposeThis paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region.Design/methodology/approachA set of top-down scanning acoustic microscope images of BGA underfill is collected and void labelled. The labelled images are trained with a convolutional neural network model, and the performance is evaluated. The model is tested with new images, and the void area with its region is analysed with its dispensing parameter.FindingsAll findings were well-validated with reference to the past experimental results regarding dispensing parameters and their quantitative regional formation. As the BGA is non-uniform, 85% of the test samples have void(s) formed in the emptier region. Furthermore, the highest rating factor, valve dispensing pressure with a Gini index of 0.219 and U-type dispensing pattern set of parameters generally form a lower void percentage within the underfilling, although its consistency is difficult to maintain.Practical implicationsThis study enabled manufacturers to forecast the void regional formation from its filling parameters and array pattern. The filling pressure, dispensing pattern and BGA relations could provide qualitative insights to understand the void formation region in a flip-chip, enabling the prompt to formulate countermeasures to optimise voiding in a specific area in the underfill.Originality/valueThe void regional formation in a flip-chip underfilling process can be explained quantitatively with indicative parameters such as valve pressure, dispensing pattern and BGA arrangement.

Pre-applied underfill Technique for Fine-pitch Cu Pillar 3D Die Stacking to Enable 2.5/3D Advanced Packaging

Increased performance and smaller form factor have driven demand for next generation architectures for integrated circuit 3D (IC) chip packaging. Advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. One key driver is the copper pillar interconnect technology which offers several benefits such as improved electromigration resistance, improved electrical and thermal conductivity, simplified under bump metallization (UBM), and higher input/output (I/O) density. The fine pitches that copper pillars are capable of helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which enhances performance. One of the major innovations has been 2.5/3D integration, a technique of vertically stacking multiple dies. However, traditional encapsulation techniques become challenging because traditional capillary underfill methods become restrictive as enlarged surface area is required in order to provide underfill protection on multiple surfaces. Here, we discuss a novel approach of vertically stacking dies with an integrated underfill process that minimizes the required area for underfilling in fine-pitch IC chip packages by creating a technique to apply underfill during thermo-compression bonding. This process offers a reliable method for vertical stacking of multiple chips and eliminates post-processing need for underfill application. Additionally, the process provides precise temperature control to both the substrate and die by using a mechanism of dual heat application. This is used in combination with a controlled variable application of compressive force on the package. Through fine-tuning of the force and temperature applied to the IC components, the bonding process can be tailored to simultaneously provide the ideal underfill curing conditions while forming solder joints. In this work, we used dies with 80µm pitch Cu pillar flip chip copper pillars with tin/silver caps bonded to Electroless Nickel and Immersion Gold (ENIG) pads in conjunction with commercially available pre-applied underfill material. The interconnect strength was determined though destructive shear testing and cross-sectional analysis to evaluate for the bonding quality and strength. A scanning electron microscope was used to visually examine joint properties, and X-ray analysis was conducted to review for underfill voiding. Finally, completed assemblies were thermal-cycled to evaluate for the degradation of joint strength and voiding of underfill under induced stress.

Surface Activation Beneath the Flip Chip by Plasma Treatments

Plasma treatment changes the surface morphology and transforms the surface energy. Therefore, it was applied before the underfill (UF) process of the flip chip to improve the wettability and adhesion of the UF and to prevent delamination or voids. This study focuses on the plasma effects of the regions beneath the flip chip, which comprise the widely used plasma gases, i.e., Ar, N2, and O2. The effects of the plasma treatments are analyzed using atomic force microscopy, X-ray photoelectron spectroscopy, and Dyne ink tests. The surface roughness of the substrate (SBT) center regions is increased from 183.9 nm (bare SBT) to 232.8 nm after the O2 plasma treatment, and the surface roughness of the die center regions is increased from 14.5 to 17.2 nm. The surface-area difference percentage also increases from 47.4% to 61.7% for the SBT center region and from 24.0% to 34.0% for the die center region. The resultant surface energy also increases from 60 to 84 mN/m for the SBT center region and from 66 to 84 mN/m for the die center region. Based on these results, it can be stated that O2 plasma is more effective than other gas plasmas for surface activation, especially beneath the die region.

Prediction of the void formation in no-flow underfill process using machine learning-based algorithm

This paper investigated the variation variables on the void formation in the no-flow underfill process. A total of 96 distinct no-flow underfill cases were numerically simulated to determine the void formations for different combinations of underfill parameters. The numerical model has been well validated with the experiment, for which the discrepancies are less than 4 %. It was found that the void formation rate increases with the chip placement speed however it decreases with the increase in bump pitch. The highest chip placement speed of 14 mm/s produces 4–6 % meanwhile, the low chip placement speed (2–5 mm/s) produces around 2–3.5 % of void formation. A supervised machine learning (ML) approach is implemented using the validated numerical results to build a prediction-based method for no-flow underfill process. Three ML methods were trained and tested. Neural networks regression was recommended compared to other methods since it has the highest R-squared value and lowest error: 0.95159 and 0.15885, respectively. Chip placement speed obtained the highest score of 1.791641 for permutation feature in ML, which indicates the most significant variable affecting the package's void formation. The obtained result will aid the industry to choose the most favourable no-flow underfill process parameters regarding the void formation issue, thus increasing the reliability of the package.

PACKAGE-ON-PACKAGE (POP) UNDERFILL PROCESS USING A MATERIAL DAM METHOD

Recent developments in the electronics industry have introduced a multi-stack ball grid array (BGA) to meet the growing consumer demand for both high-performance and smaller-sized chip packages. This study focused on the preliminary study of the Package-on-Package (PoP) underfill process using a material dam method. High viscosity type of underfill material is considered for the underfill process. In the current experimental work, L path-dispensing method was chosen due to its advantages, as reported in the previous work. The material dam method was used to prevent underfill from moving backwards and flowing out from the dispensing region. The material dam was built surrounding the PoP package. The effectiveness of the underfill process was analyzed based on the cycle time and lateral lapping, which are significant factors in material selection. The experimental results revealed that slow underfill flow may cause the quickly harden of material while the dispensing process is still running. This situation restricts the underfill flow and creates voids in the PoP package. The material dam method successfully enhanced the underfilling process for layers 3 and 4 stacked-package. This study is expected to provide the preliminary underfill process of stacking the PoP package and is useful as a reference for the engineer in the microelectronics industry.

Investigation of BGA underfill process based on multipositional computed tomography

In this paper, defect inspection related to an epoxy underfilling process between integrated circuits (ICs) and printed circuit boards (PCBs) is presented utilizing the data fusion of multipositional computed tomography (DFMCT). The work aims to verify the existence of underfilling epoxy which was not possible utilizing standard computed tomography due to strong metal artifacts created by ball grid array (BGA) packages. By interpreting the results obtained from the scanned samples, we were able to correlate the excess epoxy defects and the success of the underfilling process. We present the data fusion approach as an alternative method when traditional metal artifact reduction methods would be insufficient. The study was commenced by making a proper radiographic simulation using aRTist simulation software. The simulation enabled us to choose the right mounting positions which produce less metal artifacts for the experimental study. The DFMCT was achieved by acquiring multiple computed tomographic scans at different sample orientations. The reconstructed volumes were then aligned, and the fused volume was obtained by combining the corrected data and suppressing the disrupted data of the reconstructed volumes.

Hybrid Cu-to-Cu bonding with nano-twinned Cu and non-conductive paste

Highly (111)-oriented nanotwinned copper (nt-Cu) and non-conductive paste (NCP) were employed to fabricate hybrid Cu–Cu bonding. We tailored and correlated the fracture modes, bonding strengths, and microstructures of the joints. A non-flow underfilling process was performed, and low temperature bonding was achieved in a single heat treatment at 180 °C for 120 min without vacuum. We found that under a post-annealing treatment, recrystallization and grain growth occurred. The bonding interfaces were partially removed and the joints were further strengthened. The fracture modes of the hybrid bonding structure were characterized using pull tests and correlated with their bonding properties. Such hybrid Cu–Cu microbumps with high bonding strength and low thermal budget can be widely used for advanced ultra-fine-pitch packaging.

The study of dynamic dispensing pattern effects on capillary driven underfill process

In the present days where technology has become one of the must have items by our community, the needs of reliable electronic packaging has become crucial. This work presents the effect of different dispensing patterns on capillary driven underfill process namely I, L and U pattern in flip chip packaging. In this study, the real dynamic dispensing system that had been applied in underfilling process was simulated with a three-dimensional flip chip model that was constructed using SolidWorks and modelled using ANSYS FLUENT. As modelled, underfill material of 0.3 Pa.s viscosity was injected into a 1 mm gap of a 30x30 mm flip chip with full ball grid array package. The injection time was fixed at 3 s for all three dispensing patterns. The result obtained showed that the U pattern filled the gap the fastest followed by L pattern and I pattern but L pattern is the best due to its relatively low filling time and less void formation.

Analytical and numerical analyses of filling progression and void formation in flip-chip underfill encapsulation process

PurposeThis paper aims to study the filling progression of underfill flow and void formation during the flip-chip encapsulation process.Design/methodology/approachA new parameter of filling progression that relates volume fraction filled to filling displacement was formulated analytically. Another indicative parameter of filling efficiency was also introduced to quantify the voiding fraction in filling progression. Additionally, the underfill process on different flip-chips based on the past experiments was numerically simulated.FindingsAll findings were well-validated with reference to the past experimental results, in terms of quantitative filling progression and qualitative flow profiles. The volume fraction filled increases monotonically with the filling displacement and thus the filling time. As the underfill fluid advances, the size of the void decreases while the filling efficiency increases. Furthermore, the void formed during the underfilling flow stage was caused by the accelerated contact line jump at the bump entrance.Practical implicationsThe filling progression enabled manufacturers to forecast the underfill flow front, as it advances through the flip-chip. Moreover, filling progression and filling efficiency could provide quantitative insights for the determination of void formations at any filling stages. The voiding formation mechanism enables the prompt formulation of countermeasures.Originality/valueBoth the filling progression and filling efficiency are new indicative parameters in quantifying the performance of the filling process while considering the reliability defects such as incomplete filling and voiding.

A Surface Energy Approach to Developing an Analytical Model for the Underfill Flow Process in Flip-Chip Packaging

Abstract This paper presents a new approach to formulating an analytical model for the underfill process in flip-chip packaging to predict the flow front and the filling time. The new approach is based on the concept of surface energy along with the energy conservation principle. This approach avoids the need of modeling the flow path to predict the flow front and the filling time, and thus it is suitable to different configurations of solder bumps, including different shapes and arrangements of solder bumps in flip-chip packaging. An experiment along with the computational fluid dynamics simulation was performed based on a proprietarily developed testbed to verify the effectiveness of this approach. Both the experimental and simulation results show that the proposed approach along with its model is accurate for flip-chip packages with different configurations besides the configuration of a regular triangle arrangement of solder bumps and a spherical shape of the solder bump.

Improved yield estimation with efficient decision power for multi-line processes

Portable devices with multiple functions are commonly used in modern life, and the dies in these products have become much thinner and slimmer over time. Due to the rapid advancements in manufacturing technology in the semi-conductor industry, the process yield requirements grow increasingly strict. In advanced packaging manufacturing, the process is usually with multiple lines and often requires a very low fraction of defective. To assess the manufacturing yield precisely, the process capability index is widely used. is a generalization yield index designated for measuring the yield of multi-line processes. However, the typical existing method for obtaining the lower confidence bound of is conservative and it may mislead managers into making incorrect decisions. In this study, the nonparametric and parametric standard bootstrap methods have been implemented to establish a reliable and improved yield assessment. Three methods are investigated and the power comparison is provided. Then, two effective transformation methods to handle non-normal processes are presented and one example with simulation data is given for algorithm demonstration. Finally, an application of yield assessment for underfill processes with two manufacturing lines is presented. The simulation results demonstrate that based on the proposed method, we can reliably evaluate the true manufacturing yield and make a more powerful decision.

Underfill Flow in Flip-Chip Encapsulation Process: A Review

Abstract The scope of review of this paper focused on the precuring underfilling flow stage of encapsulation process. A total of 80 related works has been reviewed and being classified into process type, method employed, and objective attained. Statistically showed that the conventional capillary is the most studied underfill process, while the numerical simulation was mainly adopted. Generally, the analyses on the flow dynamic and distribution of underfill fluids in the bump array aimed for the filling time determination as well as the predictions of void occurrence. Parametric design optimization was subsequently conducted to resolve the productivity issue of long filling time and reliability issue of void occurrence. The bump pitch was found to the most investigated parameter, consistent to the miniaturization demand. To enrich the design versatility and flow visualization aspects, experimental test vehicle was innovated using imitated chip and replacement fluid, or even being scaled-up. Nonetheless, the analytical filling time models became more accurate and sophiscasted over the years, despite still being scarce in number. With the technological advancement on analysis tools and further development of analytic skills, it was believed that the future researches on underfill flow will become more comprehensive, thereby leading to the production of better packages in terms of manufacturing feasibility, performances, and reliability. Finally, few potential future works were recommended, for instance, microscopic analysis on the bump–fluid interaction, consideration of filler particles, and incorporation of artificial intelligence.

No-flow underfill: Effect of chip placement speed on the void formation using numerical method

No-flow underfill process can enhance the production lead time since the curing and reflow of solder interconnect and underfill are achieved simultaneously. Additionally, no-flow underfill can produce near void-free flow during the assembly process. This paper investigates the effect of chip placement speed towards the void formation of no-flow underfill process using numerical simulation and experimental methods. The findings show that the increase in chip placement speed effectively increased the gauge pressure and velocity of the underfill flow. The highest chip placement speed of 14 ​mm/s produces 12,300 ​Pa of gauge pressure and 0.1 ​m/s of underfill flow velocity. The flow profiles revealed that finger-like profile was formed above 5 ​mm/s speed during the compression process of no-flow underfill that will lead to issue of void formation in the ball grid array (BGA) region. This study recommended the usage of below 5 ​mm/s of chip placement speed to minimize the issue of finger-like formation and subsequently void formation.

Surface energetic-based analytical filling time model for flip-chip underfill process

Purpose This paper aims to present new analytical model for the filling times prediction in flip-chip underfill encapsulation process that is based on the surface energetic for post-bump flow. Design/methodology/approach The current model was formulated based on the modified regional segregation approach that consists of bump and post-bump regions. Both the expansion flow and the subsequent bumpless flow as integrated in the post-bump region were modelled considering the surface energy–work balance. Findings Upon validated with the past underfill experiment, the current model has the lowest root mean square deviation of 4.94 s and maximum individual deviation of 26.07%, upon compared to the six other past analytical models. Additionally, the current analytically predicted flow isolines at post-bump region are in line with the experimental observation. Furthermore, the current analytical filling times in post-bump region are in better consensus with the experimental times as compared to the previous model. Therefore, this model is regarded as an improvised version of the past filling time models. Practical implications The proposed analytical model enables the filling time determination for flip-chip underfill process at higher accuracy, while providing more precise and realistic post-bump flow visualization. This model could benefit the future underfill process enhancement and package design optimization works, to resolve the productivity issue of prolonged filling process. Originality/value The analytical underfill studies are scarce, with only seven independent analytical filling time models being developed to date. In particular, the expansion flow of detachment jump was being considered in only two previous works. Nonetheless, to the best of the authors’ knowledge, there is no analytical model that considered the surface energies during the underfill flow or based on its energy–work balance. Instead, the previous modelling on post-bump flow was based on either kinematic or geometrical that is coupled with major assumptions.

Effect of different temperature distribution on multi-stack BGA package

PurposeThis paper aims to determine the optimum set of temperatures through correlation study to attain the most effective capillary flow of underfill in a multi-stack ball grid array (BGA) chip device.Design/methodology/approachFinite volume method is implemented in the simulation. A three-layer multi-stack BGA is modeled to simulate the underfill flow. The simulated models were well validated with the previous experimental work on underfill process.FindingsThe completion filling time shows high regression R-squared value of up to 0.9918, which indicates a substantial acceleration on the underfill process because of incorporation of thermal delta. An introduction of 11 °C thermal delta to the multi-stacks BGA managed to reduce the filling time by up to 16.4%.Practical implicationsTemperature-induced capillary flow is a relatively new type of driven underfill designed specifically for package on package BGA components. Its simple implementation can further improve the productivity of existing underfill process in the industry that is desirable in reducing the process lead time.Originality/valueThe effect of temperature-induced capillary flow in underfill encapsulation on multi-stacks BGA by means of statistical correlation study is a relatively new topic, which has never been reported in any other research according to the authors’ knowledge.