UML State Machines Research Articles

Representing Security Specifications in UML State Machine Diagrams

Abstract Security specifications are controls and constraints on the behavior of the software and can be used to develop more secure software from the beginning. Many specification languages have been proposed to represent security specifications. However, all these specification languages are at a higher level of abstraction and can only be used to represent overall business-level design decisions. Such specifications provide guidance to the developers but do not lay out the details of the dynamic behavior that has to be implemented during the coding phase. In this paper, we propose to use UML state machine diagrams to represent detailed dynamic behavior of design-level security specifications. We argue that these behaviors when used by the developer for implementation will enable them to avoid crucial security vulnerabilities.

Correct and Cost-efficient Development of Control Systems Based on Model Integration

The increasing demands on functionality and quality of the software in control systems are in contradiction with the increasingly shorter deadlines for its development and insufficient budget. The majority of software errors occurs in the early phases of its development, but is detected in later phases of testing. Later identified errors lead to extremely high costs for their removal. To overcome these drawbacks, new approaches for development of real-time software are necessary. The main objective of this paper is to present a framework for model-driven development of control systems based on UML and reinforced with additional opportunities for an early analysis and verification of the models. For this purpose an approach for integrating UML state machine and timed automata models has been developed and used. The integration is achieved through model transformation, based on meta-models and the transformation language ATL, plug-in in Eclipse platform. The proposed approach is illustrated with a simple example for discrete-event control of air compressor system. Finally, some conclusions are made.

From UML Specification into FPGA Implementation

In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.

How to make a simple tool for verification of real-time systems

To verify real-time properties of UML statecharts one may apply a UPPAAL, toolbox for model checking of real-time systems. One of the most suitable ways to specify an operational semantics of UML statecharts is to invoke the formal model of Hierarchical Timed Automata. Since the model language of UPPAAL is based on Networks of Timed Automata one has to provide a conversion of Hierarchical Timed Automata to Networks of Timed Automata. In this paper we describe this conversion algorithm and prove that it is correct w.r.t. UPPAAL query language which is based on the subset of Timed CTL.

Consistency of UML class, object and statechart diagrams using ontology reasoners

We propose an automatic approach to analyze the consistency and satisfiability of Unified Modeling Language UML models containing multiple class, object and statechart diagrams using logic reasoners for the Web Ontology Language OWL 2. We describe how to translate UML models in OWL 2 and we present a tool chain implementing this translation that can be used with any standard compliant UML modeling tool. The proposed approach is limited in scope, but is fully automatic and does not require any expertise about OWL 2 and its reasoners from the designer.

Towards an Open Source Framework for Small Engine Controls Development

The paper describes the components of an envisioned open source framework that supports several stages in the model-based development of two- and three-wheelers software controls. The proposed solution supports the runtime execution on an OSEK-compatible [8] real-time operating system for multicore platforms. The framework consists of a modeling and simulation tool (including hierarchical state machines) and a code generator for the development of the functional model of controls and the definition of their task implementation; an OSEK/AUT OSAR operating system and device driver stack; OS and I/O configuration tools. The platform has been released open-source under an industryfriendly license. Our framework is currently in use for the development of innovative two-three wheelers control systems at Piaggio. In this paper we describe the experience matured in the application development, the benefits and current limitations of the approach. In particular, the result of this study has been a demonstrator platform which includes a BLDC motor control written using the proposed framework.

EXTENDED DISTRIBUTED UML-BASED PROTOCOL SYNTHESIS METHOD

Synthesizing specifications for real time applications that involve distributed communication protocol entities from a service specification, which is modeled in the UML state machine with composite states, is a time-consuming and labor-intensive task. Existing synthesis techniques for UML-based service specifications do not account for timing constrains and, therefore, cannot be used in real time applications for which the timing constraints are crucial and must be considered. In this paper, we address the problem of time assignment to the events defined in the service specification modeled in UML state machine. In addition, we show how to extend a technique that automatically synthesizes UML-based protocol specifications from a service specification to consider the timing constraints given in the service specification. The resulting synthesized protocol is guaranteed to conform to the timing constraints given in the service specification.

Automatization of the Instantiation Process for the Behavior of Software Product Lines

Models and model transformations constitute the basis of a set of software development techniques known as Model-Driven Development. In this context, UML State Machines have great potential for modeling the behavior of systems. In this work we are concerned with modeling the behavior of Product Lines, and their individual products. We present a process for deriving automatically a UML State Machine that models the behavior of a specific product from the UML model of a product line, via a model transformation based on Query/View/Transformation. The process directly involves the use of Feature Models in order to determine which elements of a (extended) State Machine describing a product family, will remain in the instantiation.

Extended Distributed UML-Based Protocol Synthesis Method

Synthesizing specifications for real time applications that involve distributed communication protocol entities from a service specification, which is modeled in the UML state machine with composite states, is a time-consuming and labor-intensive task. Existing synthesis techniques for UML-based service specifications do not account for timing constrains and, therefore, cannot be used in real time applications for which the timing constraints are crucial and must be considered. In this paper, we address the problem of time assignment to the events defined in the service specification modeled in UML state machine. In addition, we show how to extend a technique that automatically synthesizes UML-based protocol specifications from a service specification to consider the timing constraints given in the service specification. The resulting synthesized protocol is guaranteed to conform to the timing constraints given in the service specification.

Generation of test cases using UML models

Software Testing plays an important role in Software development because it can minimize the development cost. UML is widely used in the software development, there consists of the designing and coding of the software. Designing phase is done with the help of the UML models, which consists of the sequence diagrams, activity diagrams, use case diagrams, state chart diagrams etc. After designing of the system, the next task is coding. Since the software development is time and human resource consuming, the reduction of consumption is done with the help of the code generation automatically. This work mainly focus on the UML sequence diagram and state chart diagram as the model. We Propose a Technique for Test Case Generation using UML Models. UML models give a lot of  information that should not be ignored in testing. An innovative approach of generating test cases from the combination of UML design diagrams has been discussed in this paper. Present work used an approach where sequence diagram and state chart diagram has been used to generate test cases. The test cases thus generated are suitable for dynamic testing of system.

Internal‐to‐internal transition method for consecutive hierarchical template matching

This study proposes a method reducing the tree traversal cost by first investigating the most probable node instead of the root node when a hierarchical template matching is consecutively applied to the object. In particular, this study gives a novel viewpoint that a consecutive hierarchical template matching could be regarded as a transition of a hierarchical finite state machine, and then it proposes a novel method considering the transitions between the internal nodes of the hierarchical template tree. The proposed method is verified by applying it to pedestrian silhouette detection.

Translating UML State Machines to Coloured Petri Nets Using Acceleo: A Report

UML state machines are widely used to specify dynamic systems behaviours. However its semantics is described informally, thus preventing the application of model checking techniques that could guarantee the system safety. In a former work, we proposed a formalisation of non-concurrent UML state machines using coloured Petri nets, so as to allow for formal verification. In this paper, we report our experience to implement this translation in an automated manner using the model-to-text transformation tool Acceleo. Whereas Acceleo provides interesting features that facilitated our translation process, it also suffers from limitations uneasy to overcome.

Empirical evaluations on the cost-effectiveness of state-based testing: An industrial case study

ContextTest models describe the expected behavior of the software under test and provide the basis for test case and oracle generation. When test models are expressed as UML state machines, this is typically referred to as state-based testing (SBT). Despite the importance of being systematic while testing, all testing activities are limited by resource constraints. Thus, reducing the cost of testing while ensuring sufficient fault detection is a common goal in software development. No rigorous industrial case studies of SBT have yet been published. ObjectiveIn this paper, we evaluate the cost-effectiveness of SBT on actual control software by studying the combined influence of four testing aspects: coverage criterion, test oracle, test model and unspecified behavior (sneak paths). MethodAn industrial case study was used to investigate the cost-effectiveness of SBT. To enable the evaluation of SBT techniques, a model-based testing tool was configured and used to automatically generate test suites. The test suites were evaluated using 26 real faults collected in a field study. ResultsResults show that the more detailed and rigorous the test model and oracle, the higher the fault-detection ability of SBT. A less precise oracle achieved 67% fault detection, but the overall cost reduction of 13% was not enough to make the loss an acceptable trade-off. Removing details from the test model significantly reduced the cost by 85%. Interestingly, only a 24–37% reduction in fault detection was observed. Testing for sneak paths killed the remaining eleven mutants that could not be killed by the conformance test strategies. ConclusionsEach of the studied testing aspects influences cost-effectiveness and must be carefully considered in context when selecting strategies. Regardless of these choices, sneak-path testing is a necessary step in SBT since sneak paths are common while also undetectable by conformance testing.

Killing strategies for model‐based mutation testing

SummaryThis article presents the techniques and results of a novel model‐based test case generation approach that automatically derives test cases from UML state machines. The main contribution of this article is the fully automated fault‐based test case generation technique together with two empirical case studies derived from industrial use cases. Also, an in‐depth evaluation of different fault‐based test case generation strategies on each of the case studies is given and a comparison with plain random testing is conducted. The test case generation methodology supports a wide range of UML constructs and is grounded on the formal semantics of Back's action systems and the well‐known input–output conformance relation. Mutation operators are employed on the level of the specification to insert faults and generate test cases that will reveal the faults inserted. The effectiveness of this approach is shown and it is discussed how to gain a more expressive test suite by combining cheap but undirected random test case generation with the more expensive but directed mutation‐based technique. Finally, an extensive and critical discussion of the lessons learnt is given as well as a future outlook on the general usefulness and practicability of mutation‐based test case generation. Copyright © 2014 John Wiley & Sons, Ltd.

Towards an Ontology for UML State Machines

Ontology is a conceptual model that is used to represent the concepts in a domain and relationship between the concepts. It can be used for sharing and reuse of knowledge that allows humans and machines to exchange diverse information. UML state machines used to describe the behavior of a software systems. This article aims at to provide a solution for representing UML state machine model as an ontology expressed in OWL. a method proposed is a conceptualization of UML state machine and its operation, in order to check its consistency and its conformity. we chose OWL to represent formally our state machine augmented with SWRL rules to represent the dynamic aspect of the operation system and SPARQL to query our ontology.

Concurrent Hierarchical Finite State Machines for Modeling Pedestrian Behavioral Tendencies

A detailed and realistic simulation of pedestrian behavior requires a precise modeling of human decision making processes regarding action prioritization and selection. This paper presents a novel strategic pedestrian decision making model based on concurrent hierarchical finite state machines. The model is capable to create goal directed behavioral tendencies, which are operational guardrails for tactical models. The decision model is inherently flexible and scalable, being adaptable to different application scenarios, behavioral demands and input parameters. The applicability of the model is shown by means of an example. Furthermore, we discuss a validation and calibration approach for the decision model.

An Object-Oriented Approach To Generate Java Code From Hierarchical-Concurrent and History States

UML is widely accepted and practiced in industries for modeling and design of software systems. Software requirements and design are very important parts of software development. UML State Machine diagram is an important formalism to model the dynamic behavior of the system. In this paper, we present a new approach to generate compact and efficient Java code from complex state machine involving hierarchical-concurrent states; the proposed code can be used as a Java implementation pattern for automatic code generation for an object-oriented system. The main idea of our study is using Java Enum type with attributes for implementing complex state machines.

Estimation of Energy Consumption for Mobile Software using UML State Machine Diagram

The application software operated on mobile device like a smart phone is hard to ensure continuously provision of stable services because of limited resource like a battery. Therefore the requirements on the energy consumption of mobile software become one of critical issues in the software development. To cover the problem that the energy consumption requirement of software was not satisfied when code development is completed, we propose an energy consumption analysis technique using software design model, UML state machine diagram. The design model is transferred to Coloured Petri-Net to estimate the energy consumption. Our technique gives a chance to reduce the energy consumption in the process of software development

Accelerated model-based robustness testing of state machine implementations

In this paper, we present an approach for accelerating model-based robustness testing of state-based software components. We use the Z3 SAT solver to derive executable test cases fully automatically from a state model based on a UML Statechart. The test cases are paths along the Statechart comprising states and transitions. The main advantage of our approach is an accelerated execution of the test cases by refining already reached states as starting points for further test cases using reverse execution. Furthermore, the presented approach is able to check whether a correct target state has been reached or not when executing the path-based test cases using runtime verification and therefore increases the test significance. The runtime verification is done without instrumenting the source code of the component under test.

Hardware implementations of software programs based on hierarchical finite state machine models

Advances in microelectronic devices have dissolved the boundary between software and hardware. Faster hardware circuits that enable significantly greater parallelism to be achieved have encouraged recent research efforts into high-performance computation in electronic systems without the direct use of processing cores. Standard multi-core processors undoubtedly introduce a number of constraints, such as pre-defined operand sizes and instruction sets, and limits on concurrency and parallelism. This paper suggests a way to convert methods and functions that are defined in a general-purpose programming language into hardware implementations. Thus, conventional programming techniques such as function hierarchy, recursion, passing arguments and returning values can be entirely implemented in hardware modules that execute within a hierarchical finite state machine with extended capabilities. The resulting circuits have been found to be faster than their software alternatives and this conclusion is confirmed by numerous experiments in a variety of application areas.