Um Gate Research Articles

고출력 GaN RF 전력증폭 소자 공정 양산 개발

In this report, the results of a government supported project have been summarized. The purpose of the project was to develop a fabrication process of high power GaN RF devices with 0.4 um gate length at S-band frequency ranges. The most important fact which makes this project different from previous government funded projects on GaN HEMT device development in Korea is that this project is not only asking for the performance of the device but also for the reliability and yield of the devices which are the two crucial factors for manufacturing and mass production. Through the hard work for the last 5 years, GaN HEMT process has been developed in Wavice Inc., and it shows excellent performance and reliability. The process control monitoring devices with 0.7 mm gate periphery show −2.7 V threshold voltage, >200V breakdown voltage, 950 mA/mm maximum saturation current, 250 mS/mm maximum trans-conductance, 19 GHz ft, 41 GHz fmax, 16.5 dB small signal gain, 8W/mm maximum output power density, 53% power added efficiency. The RF performances of PCM devices were measured with continuous wave mode. The high power devices were fabricated by connecting unit cell devices with 3.5 mm gate periphery in parallel. 3.5 mm devices show >20W output power and 3.5x8=28 mm devices show >186.5W output power, >13.5dB small signal gain, >63.5% drain efficiency over 400 MHz bandwith in S-band with pulsed input signal with 15% duty cycle.. Both unit cells and 180W high power devices passed MIL-STD based reliability tests. The 180W devices shows 83~92% yield from the on wafer test.

Characteristics of enhanced-mode AlGaN/GaN MIS HEMTs for millimeter wave applications

In this paper, an enhanced-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) was developed by using 4-inch GaN HEMT process. We designed and fabricated Emode HEMTs and characterized device performance. To estimate the possibility of application for millimeter wave applications, we focused on the high frequency performance and power characteristics. To shift the threshold voltage of HEMTs we applied the Al2O3 insulator to the gate structure and adopted the gate recess technique. To increase the frequency performance the e-beam lithography technique was used to define the 0.15 um gate length. To evaluate the dc and high frequency performance, electrical characterization was performed. The threshold voltage was measured to be positive value by linear extrapolation from the transfer curve. The device leakage current is comparable to that of the depletion mode device. The current gain cut-off frequency and the maximum oscillation frequency of the E-mode device with a total gate width of 150 um were 55 GHz and 168 GHz, respectively. To confirm the power performance for mm-wave applications the load-pull test was performed. The measured power density of 2.32 W/mm was achieved at frequencies of 28 and 30 GHz.

Design and Simulation Noise Characteristics of AlGaN/GaN HEMT on SIC Substrate for Low Noise Applications

In this study, AlGaN/GaN high electron mobility transistor (HEMT) with 0.25 um gate-length have been designed on an SIC-4H substrate. DC and Noise characteristics of AlGaN/GaN HEMT with 0.25 um gate- length at microwave frequencies have been explored. The simulation has been performed by using the Silvaco software. The extrinsic transconductance of the device was 215 ms/mm. Also, device exhibited current drive capability as high as 1400 ma/mm. The device has demonstrated high unity current gain cut-off frequency (ft) of 100 GHz. The microwave noise characteristics of the device were determined from 0 to 20 GHz at different drain biases and drain currents. At a gate bias of -4 V and drain bias of 10 V, device exhibited a minimum noise figure (NFmin) of 0.41 dB and maximum associated gain (Gma) of 19.95 dB at 10 GHz. The noise resistance of device is 27.2 ohm at 10 GHz, which is very suitable for low noise applications in X-band frequency range. These results indicates the capability of AlGaN/GaN HEMT for low noise and high power amplifiers.

Thermally stable In0.7Ga0.3As/In0.52Al0.48As pHEMTs using thermally evaporated palladium gate metallization

This work described the fabrication and performances of strained channel In0.52Al0.47As/In0.7Ga0.3As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 °C for 35 min, a 10 nm Pd-gate device displays a VTH of −0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing VTH = −0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm−1 (from 500 mS mm−1), a high IDSmax of 400 mA mm−1 (from 330 mA mm−1) and good fT and fmax of 24.5 and 49 GHz commensurate with the 1 µm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 °C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.

Moisture Reliability Improvement of a High Performance Depletion Mode 0.15 um Gate PHEMT Process

Moisture reliability of a 0.15-um gate PHEMT technology for mm-wave applications was investigated. The PHEMT technology is fabricated with a deep UV optical lithography, and typically exhibits transconductance of ~550 mS/mm and fT of ~90 GHz. Moisture reliability, THBL or BHAST performed at 85% relative humidity, and 95 °C, or 130 °C and 85% RH, respectively, initially showed failures up to 70%, under various process splits. Extensive failure analysis pointed to a number of mechanisms contributing to failure, the key culprit being moisture ingress, enabled by poor quality of SiN, stresses, seams, and voids in the passivation dielectric around the gate topology. Moisture penetrated the SiN to GaAs surface through seams in the dielectric around the gate or regions of high local stress such as gate feeds and ends. A corrosion process ensued with the applied voltage bias on the device drain and gate during the THBL or BHAST environmental stress, leading to GaAs oxidation, metal migration and shorts. By designing the gate topology appropriately, failures were reduced to the range of 0–3.4 %. Further, using a BCB overcoat, failures were completely eliminated.

GaN HEMT Reliability: From Time Dependent Gate Degradation to On-state Failure Mechanisms

ABSTRACTIn this paper, we compare degradation modes and failure mechanisms of different AlGaN/GaN HEMT technologies. We present data concerning reverse-bias degradation of GaN-based HEMTs, which results in a dramatic increase of gate leakage current, and present a timedependent model for gate degradation. Some of the tested technologies demonstrated to be immune from this failure mechanism up to drain-gate voltages in excess of 100 V. When this was the case, the main failure mode consisted of drain current degradation during on-state tests, resulting from charge trapping in the gate-drain access region attributed to hot-electron effects. Finally, the use of diagnostic techniques such as electroluminescence microscopy and Deep Level Transient Spectroscopy for the identification of failure modes and mechanisms of GaNbased HEMTs is reviewed. Concerning reverse-bias degradation of GaN-based HEMTs, we demonstrate that, (i) when submitted to reverse-gate stress, HEMTs can show both recoverable and permanent degradation. (ii) recoverable degradation consists of a decrease in gate current and threshold voltage, which are ascribed to the simultaneous trapping of negative charge in the AlGaN layer, and of positive charge close to the AlGaN/GaN interface. (iii) permanent degradation is manifested by the generation of parasitic leakage paths. Time-dependent analysis suggests that permanent degradation can be ascribed to a defect generation and percolation process. Results supports the existence of a time to breakdown for HEMT degradation, which significantly depends on the stress voltage level. On the contrary, AlGaN/GaN technologies which were found to be resistant to gate degradation (off-state critical voltage larger than 100 V for a 0.25 um gate device) were subjected to on-state tests at different gate and drain voltage levels. All tests showed a non-recoverable degradation of electrical parameters (drain saturation current, threshold voltage and on-state resistance) and electroluminescence signal EL, with a strong dependence on the EL value of the bias point, and a negligible dependence of temperature. Once verified that EL intensity represents a reliable estimate of channel hot electron effects, we attributed the degradation to hot electron trapping in the gate-drain access region. Using EL intensity as a measure of the stress acceleration factor, we derived an acceleration law for GaN HEMT hot electron degradation similar to the one already demonstrated for GaAs devices.

UV Responsive Characteristics of n-Channel Schottky Barrier MOSFET with ITO as Source/Drain Contacts

Abstract We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) tothe source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10
um gate length and 100
um gatewidth, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the I DS -V GS characteristics at alow drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at V DS =3 V. Weobserved that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejectionratio was about 130 at V DS = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highlyapplicable to the UV image sensors. Keywords : Highly resistive GaN, Schottky Barrier MOSFET, ITO, UV responsivity 1. INTRODUCTION Gallium nitride(GaN) is one of the most promisingmaterials for both opto-electronic devices, such as highsensitive ultraviolet(UV) detector, visible light emissiondiode(LED) and high temperature / high frequency / highpower electronic devices, such as high electron mobilitytransistor(HEMT)[1-3], metal insulator semiconductorfield effect transistor(MISFET)[4, 5].At least until recently, there has not been much interestin enhancement mode transistors, even though there aremany applications for integrated UV image sensors as wellas high power logic integrated circuit applications.Schottky barrier source/drain(S/D) structure MISFET andsilicon implanted S/D MISFET have been presented in [6]and [7], respectively. The schottky barrier S/D is anattractive solution because it excludes the use of the highcost S/D ion implantation process and very hightemperature activation at over 1500 \C[1]. Indium-tin-oxide(ITO), on the other hand, has been widely applied tomany other opto-electronic devices because of its highlyconductive and visible-transparent properties[8].In this study, we investigated both the electrical and theUV responsive characteristics of a fabricated enhancementmode n-channel SB-MOSFET using ITO schottky barrierS/D on a highly resistive GaN layer grown on a siliconsubstrate in the near UV and visible regions for the variousgate/drain bias conditions. The fabricated devices exhibitvery promising behaviors, such as a very high on/offcurrent ratio, high transconductance, and a goodUV/visible rejection ratio.

The AC-Bias Stability of Short Channel a-Si:H TFT

The AC-bias stress was applied at 2um gate length a-Si:H TFT and 4.2um gate length a-Si:H TFT respectively in order to investigate the stability of short channel a-Si:H TFT. The peak voltage of applied AC bias was 7.5 V and the base voltage of it was -7.5 V respectively. The AC bias stress was applied for 100,000 seconds at 60oC. The VTH of short channel a-Si:H TFT was decreased about 0.34V after the AC bias stress while that of long channel a-Si:H TFT was increased about 0.20V. Because the VTH of short channel a-Si:H TFT was less increased than that of long channel a-Si:H TFT during on state period the increase of short channel a-Si:H TFT was compensated more efficiently than that of long channel one at off sate period. Our experimental result showed that the AC stability of short channel a-Si:H TFT was better than that of long channel one.

NON-VOLATILE HIGH SPEED & LOW POWER CHARGE TRAPPING DEVICES

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO 2/ SiO 2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO 2/ SiO 2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ~0.44 eV for the write process and ~0.47 eV for the erase process in SiO 2/ SiO 2 structural device which is somewhat more efficient than those of SONOS structure memory.