Ultrathin Transistors Research Articles

MD simulations of low energy Clx+ ions interaction with ultrathin silicon layers for advanced etch processes

Molecular dynamics simulations of low-energy (5–100 eV) Cl+ and Cl2+ bombardment on (100) Si surfaces are performed to investigate the impact of plasma dissociation and very low-energy ions (5–10 eV) in chlorine pulsed plasmas used for silicon etch applications. Ion bombardment leads to an initial rapid chlorination of the Si surface followed by the formation of a stable SiClx mixed layer and a constant etch yield at steady state. The SiClx layer thickness increases with ion energy (from 0.7 ± 0.2 nm at 5 eV to 4 ± 0.5 nm at 100 eV) but decreases for Cl2+ bombardment (compared to Cl+), due to the fragmentation of Cl2+ molecular ions into atomic Cl species with reduced energies [one X eV Cl + <−> two 2X eV Cl2+]. The Si etch yield is larger for Cl2+ than Cl+ bombardment at high-energy (Ei > 25 eV) but larger for Cl+ than Cl2+ bombardment at low-energy (Ei < 25 eV) due to threshold effects. And the higher the ion energy, the less saturated the etch products. Results suggest that weakly dissociated chlorine plasmas (containing more Cl2+ than Cl+ ions) should lead to thinner SiClx mixed layers and lower Si etch yields if ion energies remains below 25 eV, which confirms the potential of pulsed plasmas to address etching challenges of ultrathin films transistors, in which slow etch rates and very controlled processes are required.

Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node

In this paper we investigate the Total Ionizing Dose (TID) response of an UltraThin Buried-OXide (UTBOX) on a Fully Depleted Silicon-On-Insulator (FDSOI) high-k/metal gate technology. The impact of thinning the BOX and of the use of a Ground Plane (GP) at the back side of the BOX on the TID behavior are discussed by comparing their results to ionizing radiation experiments performed on reference FDSOI devices.

ADVANCED CONCEPTS FOR FLOATING-BODY MEMORIES

With 30nm-class memory cells in production and 20nm-class (20-29nm feature-size) memory targeted for next year, the standard 1-Transistor + 1-Capacitor (1T+1C) DRAM industry is making prominent efforts to improve the scalability of the cell capacitor while maintaining the minimum capacitance requirements for state discrimination, immune to noise (C~25fF/cell). To achieve the capacitance requirement, the DRAM cell has evolved from its initial planar implementation to complex three-dimensional structures. The increment in complexity and the large difference in size between the transistor and capacitor of each cell have motivated the search for Floating-Body Single-Transistor DRAM (1T-DRAM). The underlying idea behind 1T-DRAMs is the development of single-device memory cells with a pronounced hysteresis effect and fast operation. This chapter is focused on the floating-body effect as a primary source of hysteresis. We present new concepts able to deal with the basic limitations of 1T-DRAM while maintaining its simplicity. The floating-body 1T-DRAMs can be reconciled with the aggressive scaling constrains by considering new ideas which make possible the coexistence of electron and holes in the same ultrathin transistor. The best approach is to isolate each type of carrier in an specific potential well which is not created specifically by the bias conditions (unlike standard 1T-DRAMs) but by the physical structure of the device.

Calcium Ion Detection Using Miniaturized InN-based Ion Sensitive Field Effect Transistors

An Ultrathin (~10 nm) InN ion sensitive field effect transistor (ISFET) with gate regions functionalized with phosphotyrosine (p-Tyr) is proposed to detect calcium ions (Ca 2+ ) in aqueous solution. The ISFET was miniaturized to a chip size of 1.1 mm by 1.5 mm and integrated at the tip of a hypodermic injection needle (18 G) for real-time and continuous monitoring. The sensor shows a current variation ratio of 1.11% with per decade change of Ca 2+ and a detection limit of 10-6 M. The response time of 5 sec. reveals its great potential for accomplishing fast detection in chemical and physiological sensing applications. The sensor would be applied in medical diagnosis and used to monitor continuous and real-time variations of Ca 2+ levels in human blood in the near future.

Electron spin resonance observation of field-induced charge carriers in ultrathin-film transistors of regioregular poly(3-hexylthiophene) with controlled in-plane chain orientation

Ultrathin-film polymeric transistors with controlled in-plane chain orientation have been fabricated based on Langmuir–Blodgett technique by cospreading liquid crystal molecule with regioregular poly(3-hexylthiophene). The mobilities parallel to the chain direction reached 0.001–0.01 cm2/V s for 1 to 5 monolayer thick transistors. Mobility ratio was about 2 for the parallel and perpendicular directions. Electron spin resonance (ESR) signals of the field-induced polarons exhibited clear in-plane anisotropies due to unpaired π-electrons. The anisotropic ESR spectra together with the optical dichroism determine the detailed molecular orientations in the channel of such ultrathin transistors.

Hole Mobility in Ultrathin Double-Gate SOI Devices: The Effect of Acoustic Phonon Confinement

We show that the effect of phonon confinement in ultrathin double-gate silicon-on-insulator (DGSOI) transistors on hole mobility is weaker than that predicted for electron mobility. To do so, confined phonon modes in SOI devices are computed, employing an elastic continuum model of acoustic phonons in a three-layer structure. A self-consistent k middot p-Poisson solver has been developed for the valence-band structure calculation, and Kubo-Greenwood formalism is used to compute the hole mobility in ultrathin DGSOI transistors under the combined effect of confined phonon and surface-roughness scattering.

Improving Switching Performance of Thin-Film Transistors in Disordered Silicon

The silicon integrated electronics on glass or plastic substrates attracts wide interests. The design, however, depends critically on the switching performance of transistors, which is limited by the quality of silicon films due to the materials and substrate process constraints. Here, the ultrathin channel device structure is proposed to address this problem. In a previous work, the ultrathin channel transistor was demonstrated as an excellent candidate for ultralow power memory design. In this letter, theoretical analysis shows that, for an ultrathin channel transistor, as the channel becomes thinner, stronger quantum confinement can induce a marked reduction of OFF-state leakage current (IOFF), and the subthreshold swing (S) is also decreased due to stronger control of channel from the gate. Experimental results based on the fabricated nanocrystalline silicon thin-film transistors prove the theoretical analysis. For the 2.0-nm-thick channel devices, ION/IOFF ratio of more than 1011 can be achieved, which can never be obtained for normal thick channel transistors in disordered silicon.

Evidence for mobility enhancement in double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors

The methodology of mobility extraction from the Y-function or from the transconductance peak is revisited in the context of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on a simple two-channel model, we discuss the biasing conditions that enable the Y-function to be applied to both single-gate (SG) and double-gate (DG) modes. Systematic mobility measurements in thick and ultrathin SOI transistors are presented for the front channel, back channel, and in quasi-double-gate mode. In SG-mode, the mobility is overestimated as soon as the opposite channel is activated. In partially depleted or relatively thick, fully depleted MOSFETs, the two channels are separated; hence, the total apparent mobility in DG mode is the sum of the front and back channel mobilities. By contrast, the two-channel model fails in ultrathin transistors, where the two channels become strongly coupled and volume inversion occurs. Volume inversion is reflected in a remarkable increase of the apparent mobility in DG mode.

Ultrathin organic transistors for chemical sensing

Ultrathin cobalt phthalocyanine transistors of 4 ML have been fabricated for chemical sensing. Compared to 50 ML devices, the ultrathin transistors show faster response times, higher base line stabilities, and sensitivity enhancements of 1.5–20 for the five analytes tested. The enhanced response for the ultrathin transistors provides insight into the device physics. The absorption of analytes changes the surface doping level and trap energies. The changes in surface trap energies perturb the charge transport properties of the ultrathin devices, thereby, making these devices more sensitive.

Computational modeling of process induced damage during plasma clean

When partially completed circuits come in contact with plasmas during integrated circuit fabrication, current from the plasma can potentially damage active devices on the wafer. A suite of computational models is used in this article to investigate damage to ultrathin (1.0–5.5nm) transistor gate dielectric (SiO2) during Ar∕O2 based plasma cleaning in a capacitively coupled plasma reactor. This modeling infrastructure includes a two-dimensional plasma equipment model for relating process control parameters to ion and electron currents, a three-dimensional model for flux density calculation within a circular via, an electrostatic model for computing potential across the gate dielectric, and a percolation model to investigate dielectric damage characteristics. Computational results show that when the plasma current comes in contact with the gate dielectric, the gate dielectric rapidly charges up and the potential difference across the dielectric saturates at the level necessary to support the plasma induced current. The steady-state voltage across the dielectric determines the propensity of irreversible damage that can occur under this electrical stress. Gate dielectric damage was found to be most sensitively linked to dielectric thickness. As thin dielectrics (<2.0nm) are leaky, direct tunneling current flow ensures that the potential drop across the gate dielectric remains small. As a consequence, the dielectric is able to withstand the plasma current and the probability of damage is small. However, for thicker dielectrics where Fowler-Nordheim tunneling is dominant, a large voltage builds up across the gate dielectric due to the plasma induced current. The probability of thicker dielectrics getting damaged during the plasma process is therefore high. For given plasma conditions and gate dielectric thickness, current collection area (i.e., antenna size) determines the voltage buildup across the gate dielectric. Damage probability increases with the size of the antenna connected to the transistor gate electrode. Via aspect ratio and plasma process condition variations (around a given set of process conditions) have a relatively smaller effect on plasma induced device damage.

Increase in carrier mobility of organic ultrathin-film transistor with increasing molecular layers investigated by Kelvin probe force microscopy

Organic ultrathin transistors with a 3-μm-length channel were fabricated using dimethylquinquethiophene molecules. The local structures of the films and electric potential profiles across the channels were investigated by Kelvin probe force microscopy with the gate electrode grounded. We found that the local carrier mobility was much higher for the second-layer regions than for the monolayer regions from potential profiles measured while the gate electrode was electrically grounded. However, the macroscopic carrier mobility increased only slightly by increasing the number of molecular layers. One of the possible reasons for this contradiction was the large contact resistance at the source∕channel interface, which was apparently observed in the potential profiles.

Polarity Dependence of Degradation in Ultra Thin Oxide and JVD Nitride Gate Dielectrics

AbstractWe have studied high field degradation of Jet Vapor Deposited (JVD) silicon nitride MNSFETs with DC stress fields and compared their degradation with conventional silicon dioxide MOSFETs under identical stress conditions. We have observed that in both oxide and nitride devices, the interface degradation is higher for negative gate field. Further, the relative degradation of nitrides is always lower compared to that of oxides for both positive and negative stress conditions. AC stress experiments were performed on these ultra thin oxide transistors to understand possible degradation processes. The frequency, the peak-to-peak and offset voltage of the applied AC signal are some of the parameters that have been varied. Detailed characterization results and an analysis of the degradation mechanisms are presented in this paper. We conclude that many of the degradation results can be explained using the trapped hole recombination model.

Modeling of direct tunneling and surface roughness effects on C–V characteristics of ultra-thin gate MOS capacitors

Effects of direct tunneling and surface roughness on the capacitance–voltage characteristics of ultra-thin gate deep submicron MOS transistors have been studied. An improved equivalent circuit model to account for surface roughness and direct tunneling on the ultra-thin gate MOS capacitors in a unified manner is proposed. The capacitance subject to direct tunneling and surface roughness effect is smaller than that without surface roughness effect.

Modes of operation and radiation sensitivity of ultrathin SOI transistors

Improved short-channel behavior, reduced subthreshold slopes, and mobility enhancements previously observed in NMOS transistors made in thin, fully depleted silicon-on-insulator (SOI) films are discussed. These results were obtained with the back interface held in depletion during operation. It is shown from basic principles of device operation that the observed performance improvements are sensitive to the applied substrate voltage. In addition, the exposure of the back interface to the surface depletion region in these devices makes the transistor performance sensitive to radiation-induced charging effects at the back interface. The anticipated effects of radiation on threshold voltage, subthreshold slope, and mobility in ultrathin, fully depleted SOI transistors are discussed, and an estimate is made of the expected radiation sensitivity of these parameters for a typical ultrathin SOI technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4*10/sup 16/ cm/sup -3/, the drain saturation current in ultrathin SOI transistors is predicted to be approximately 40% larger than that of bulk structures. An increase of approximately 30% is seen in measurements made on devices in 1000-A SOI films.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Molecular beam epitaxially grown circular U-groove barrier transistor

A new version of simple GaAs n+-n-δ(p+)-n-n+ ultrathin base transistor with U-groove base contact is demonstrated by molecular beam epitaxy which possesses a circular mesa etched base. The potential barrier height can be directly modulated by the applied base voltage and thus the current can traverse over the barrier by thermionic emission. It is a voltage-controlled device. Its transconductance increases with increasing collector-emitter and base-emitter voltage. The collector current density of the present device is larger than 1.5 kA/cm2 and the transconductance is larger than 200 mS/mm, which are larger than those of the previously reported V-groove device.