Ultra-thin Body Silicon-on-insulator MOSFETs Research Articles

Sensitivity Analysis of the UTBSOI Transistor based Two-Stage Operational Amplifiers

In the nanoscale domain, the MOSFETs are prone to various physical effects due to their shorter channel region known as short-channel effects (SCE). The researchers have proposed an advanced structure of MOSFET known as the ultrathinbody silicon-on-insulator (UTBSOI) to overcome the limitations of SCEs. The UTBSOI is a type of double-gate (DG) MOSFET having superior controllability of gates over the shorter channel region. Nowadays, the UTBSOI MOSFETs can be adopted in the circuit simulators through the use of a device model named BSIM-IMG. The BSIM-IMG has made it possible for the circuit designers to simulate any UTBSOI based analog blocks like operational amplifiers (opamp). The performance parameters of an opamp are very much sensitive to any perturbation in size (W/L) of the constituent MOSFETs, that may cause a drastic change in the output. In this paper, the sensitivity analysis procedure has been proposed for the CMOS and UTBSOI based two-stage opamps as the function of perturbation in W/L. In addition to this, an algorithm has also been presented to do the same. From the simulation results, it is observed that the sensitivity of the UTBSOI based opamp (UTBSOI-opamp) is larger than that of CMOS based opamp (CMOS-opamp).

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

A review of special gate coupling effects in long-channel SOI MOSFETs with lightly doped ultra-thin bodies and their compact analytical modeling

The charge coupling between the front and back gates is a fundamental property of any fully-depleted silicon-on-insulator (SOI) MOSFET. It is traditionally described by the classical Lim and Fossum model (Lim and Fossum, 1983). However, in the case of lightly-doped ultra-thin-body (UTB) SOI MOSFETs with ultra-thin gate dielectrics, significant deviations from this model have been observed and analyzed over the years. In this paper, we present a thorough review of special features of gate coupling in such devices, combining a large set of results from one-dimensional numerical simulations in classical and quantum–mechanical modes, experimental data and analytical modeling. We show that UTB SOI MOSFETs with ultra-thin gate dielectrics feature stronger modulation of the threshold voltage at the conduction side with opposite gate bias and much wider range of gate voltages for interface coupling than predicted by the Lim and Fossum model. These differences originate from both electrostatic and quantization effects. A simple analytical model taking into account these effects is presented. The model enables an easy assessment of the quantization-induced threshold voltage increase in a long-channel SOI MOSFET versus opposite gate bias and the electric field in the silicon film associated with gate decoupling.

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility

This paper presents a study of the effect of the gate-voltage-dependent mobility on the threshold voltage extraction in long-channel MOSFETs by the transconductance change method and recently proposed transconductance-to-current ratio change method, using analytical modeling and experimental data obtained on advanced silicon-on-insulator (SOI) FinFETs and ultrathin-body SOI MOSFETs with ultrathin high- gate dielectrics. It is shown that, at vanishingly small drain voltage and constant mobility, both methods yield the same values, coinciding with the position of the maximum of the second derivative of the inversion carrier density in respect to the gate voltage. However, such is not the case anymore when considering gate-voltage dependence of mobility around threshold. Analytical expressions for the errors in the values obtained by both methods due to mobility variation around threshold are obtained. Based on analytical modeling and experimental data, it is demonstrated that, for the same mobility variation, the resulting error on the extraction caused by the gate-voltage-dependent mobility is much smaller for the transconductance-to-current ratio change method than for the transconductance change method.

Analysis of subthreshold conduction in short-channel recessed source/drain UTB SOI MOSFETs

Abstract The subthreshold conduction regime in short-channel recessed source/drain (ReS/D) ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFETs is studied. A physics-based model for the subthreshold slope of ReS/D UTB SOI MOSFETs is developed, based on an analytical solution of 2-D Poisson’s equation for the front-gate and back-gate potential distributions. In order to verify the accuracy of the model, the calculated subthreshold slope values are compared with the results obtained by Medici 2-D numerical device simulator over a wide range of different device structures, and very good agreement is obtained down to channel lengths of sub-30 nm. The model is given in explicit form without any fitting parameters and requires no iterative calculation, thus making it ideally suitable for fast prediction and evaluation of device design criteria for optimal scaling of the ReS/D UTB SOI MOSFETs.

Mobility extraction in SOI MOSFETs with sub 1 nm body thickness

In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem. Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.

Optimum location of silicide/Si interface in ultra-thin body SOI MOSFETs with recessed and elevated silicide source/drain contact structure

Optimization of the series resistance of silicide contact structure in ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFET with elevated source/drain (S/D) is examined through theoretical analysis and 2-dimensional simulation. It is found that the optimum silicide/Si interface position, which exhibits lowest parasitic series resistance, can be located at inside of SOI layer under the surface as the effective contact length is scaled down further below 100 nm regime. The closed-form analytical expressions derived from modified transmission line model principle provide a guideline for optimum design of silicide thickness and contact parameters in self-aligned silicide technology.

Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs

Front-gate and back-gate potential distributions and threshold voltage of recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are modeled. The analytical expressions of the front-gate and the back-gate potential distributions are derived by assuming a parabolic potential variation perpendicular to channel and by solving 2D Poisson’s equation. Based on strong inversion criterion applied to the surface potential minimum value, threshold voltage model of the short channel ReS/D UTB SOI MOSFETs is derived. The model is verified by comparison with 2D numerical device simulator over a wide range of different material and geometrical parameters and very good agreement is obtained.

Performance Prediction of Graphene-Channel Field-Effect Transistors

We compare the threshold voltage and subthreshold-slope characteristics as measures of short-channel effects (SCEs) for graphene-channel field-effect transistors (GFETs) with wide bilayer armchair-graphene film with those for ultrathin-body silicon-on-insulator (UTB-SOI) MOSFETs using a drift-diffusion-based device simulator. The intrinsic delay times for GFETs are also compared with those for UTB-SOI MOSFETs.

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.

Tradeoff between speed and static power dissipation of ultra-thin body SOI MOSFETs

The speed performance and static power dissipation of the ultra-thin-body (UTB) MOSFETs have been comprehensively investigated, with both DC and AC behaviours considered. Source/drain extension width (Lsp) and silicon film thickness (tsi) are two independent parameters that influence the speed and static power dissipation of UTB silicon-on-insulator (SOI) MOSFETs respectively, which can result in great design flexibility. Based on the different effects of physical and geometric parameters on device characteristics, a method to alleviate the contradiction between power dissipated and speed of UTB SOI MOSFETs is proposed. The optimal design regions of tsi and Lsp for low operating power and high performance logic applications are given, which may shed light on the design of UTB SOI MOSFETs.