UltraScale Field Programmable Gate Array Research Articles

TCLink: A Fully Integrated Open Core for Timing Compensation in FPGA-Based High-Speed Links

The high luminosity expected in the second phase of the upgrades of the Large Hadron Collider (LHC phase-2 upgrades) will pose unprecedented challenges to its four experiments in terms of collisions density – also known as pileup – per beam crossing. Disentangling the vertices of 200 simultaneous collisions every 25 ns requires high granularity in the detectors, as well as extremely precise and stable timing. While short-term timing stability is usually a concern addressed in timing distribution systems, long-term variations due to changing environmental conditions can accumulate through distribution chains and can dominate the overall timing stability of the systems they serve. Timing distribution systems in LHC experiments typically use high-speed links and clock recovery. This paper presents a logic core that can be used to mitigate long-term temperature variations in high-speed links. The Timing Compensated Link (TCLink) is an open-source firmware core fully integrated in Xilinx Ultrascale Field Programmable Gate Arrays (FPGAs). It demonstrates picosecond-level phase precision over timing distribution systems, improving the overall timing stability in physics experiments.

FPGA acceleration on a multi-layer perceptron neural network for digit recognition

This paper proposes field-programmable gate array (FPGA) acceleration on a scalable multi-layer perceptron (MLP) neural network for classifying handwritten digits. First, an investigation to the network architectures is conducted to find the optimal FPGA design corresponding to different classification rates. As a case study, then a specific single-hidden-layer MLP network is implemented with an eight-stage pipelined structure on Xilinx Ultrascale FPGA. It mainly contains a timing controller designed by Verilog Hardware Description Language (HDL) and sigmoid neurons integrated by Xilinx IPs. Finally, experimental results show a greater than $$\times 10$$ speedup compared with prior implementations. The proposed FPGA architecture is expandable to other specifications on different accuracy (up to 95.82%) and hardware cost.

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

This article proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\bf DN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\bf IN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$</tex-math></inline-formula> are close to or even less than 0.05 LSB in multichannel designs.

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power‐efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power‐efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

Environment-friendly FSM design on ultra-scale architecture: energy-efficient green computing approach

PurposeThe Purpose of this research is to make an energy efficient finite state machine (FSM) in order to achieve the core objective of green computing because FSM is an indispensable part of multiple computer hardware.Design/methodology/approachThis study uses ultra-scale plus FPGA architecture in place of seven-series field-programmable gate array (FPGA) for the implementation of the FSM design and also uses output load scaling for the design of environment-friendly FSM. This design study is done using Verilog Hardware description language and Vivado integrated system environment design tools and implemented on 16 nm ultra-scale FPGA architecture.FindingsThere is up to 98.57% reduction in dynamic power when operating frequency is managed as per smart job scheduling. There is up to a 21.97% reduction in static power with proper management of output load capacitance. There is up to 98.43% saving in dynamic power with the proposed management of output load capacitance.Originality/valueThe proposed design will be environment friendly that eventually leads to the green earth. This is the main motive of the research area i.e. green computing.

Achieving Picosecond-Level Phase Stability in Timing Distribution Systems With Xilinx Ultrascale Transceivers

This article discusses the challenges posed on the field-programmable gate array (FPGA) transceivers in terms of phase-determinism requirements for timing distribution at the Large Hadron Collider (LHC) experiments. Having a fixed phase after startups is a major requirement, and the typical phase variations observed in the order of tens of picoseconds after startups while using the state-of-the-art design techniques are no longer sufficient. Each limitation observed in the transmitter and receiver paths of the high-speed transceivers embedded in the Xilinx Ultrascale FPGA family is further investigated and solutions are proposed. Tests in hardware using Xilinx FPGA evaluation boards are presented. In addition to a higher phase determinism, the techniques presented make it possible to fine-tune the skew of a link with a picosecond resolution, greatly simplifying clock-domain crossing inside the FPGAs and providing better short-term stability for the FPGA-recovered clock in a high-speed link.

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

Extracting discriminative k-mers is an important and challenging problem in DNA sequence analysis with applications in metagenomics and motif discovery. Despite the availability of multiple computational tools designed for this purpose, most discriminative k-mer discovery methods suffer from long execution times and high memory usage when processing large datasets. This paper presents a novel approach for discriminative k-mer discovery in DNA sequences, which leverages streaming and sketch algorithms to reduce space complexity and expose data parallelism, enabling the use of parallel platforms for accelerating the execution of computationally-intensive operations. To assess the performance of our method, we designed and implemented two versions of the algorithm that leverage parallelization at different levels: (i) a software version tailored for multithreading and vector instructions in commodity CPUs, and (ii) a custom architecture implemented on a Field-Programmable Gate Array (FPGA) accelerator that exploits fine-grain parallelism and deep pipelining on reconfigurable logic. Experimental results show that, when mining discriminative k-mers from a set of well-known ChIP-seq sequences, our parallel software implementation executes at least 15% faster than exact-counting tools, and requires at least five times less memory when processing large datasets. More importantly, we designed a custom FPGA-based accelerator for our algorithm on a Xilinx KCU1500 board, which achieves speedups above 78x with the largest datasets, compared to our parallel software implementation. The accelerator uses less than 3% of the logic resources available on the on-board XCKU115 Kintex-7 Ultrascale FPGA, and between 12% and 70% of the memory resources, depending on the size of the dataset.

A High-Precision 2.5-ps RMS Time Synchronization for Multiple High-Speed Transceivers in FPGA

The high-speed serial transceiver plays a key role in the high-speed data transmission. Because of the independent clock network in each transceiver, there exist random skews between the multiple transceivers each time the system reinitializes. In the system of data transmission, these random skews are always permitted and the intrachannel synchronization is guaranteed by inserting some same comma codes in each channel. However, for the strict clock distribution system, these random skews are unacceptable. To address this problem, a scheme combined of a tunable phase interpolator (PI) and a high-precision time-to-digital converter (TDC) is presented. A plain TDC is employed to measure the skews of parallel clocks in multichannels with bin size of ~10.2 ps and precision of ~18.0 ps. The method of multiple measurements average is adopted to further improve the TDCs performance. On this basis, time synchronization with root mean square (rms) of ~2.5 ps and peak-to-peak value of ~14.7 ps is implemented in a 20-nm fabrication process ultrascale field programmable gate array (FPGA). Compared to the measured results (rms of ~22 ps and peak-to-peak value of ~105 ps) of the Xilinx self-phase alignment method, the presented scheme has more than six times performance improvement. In addition, this scheme can lock the delay between different channels to arbitrary configurable offsets, making it very suitable for scenarios where multichannel latencies are strictly restricted.

Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs

This paper presents low nonlinearity, compact, and multichannel time-to-digital converters (TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays (FPGAs). The proposed TDCs integrate several innovative methods that we have developed: 1) the subtapped delay line averaging topology; 2) tap timing tests; 3) a direct compensation architecture; and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25% of the logic resources. The achieved least significant bit (LSB) is 10.5 ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [–0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [–0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [–0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [–0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

The increase of luminosity at the HL-LHC will require the introduction of tracker information in CMS’s Level-1 trigger system to maintain an acceptable trigger rate when selecting interesting events, despite the order of magnitude increase in minimum bias interactions. To meet the latency requirements, dedicated hardware has to be used. This paper presents the results of tests of a prototype system (pattern recognition ezzanine) as core of pattern recognition and track fitting for the CMS experiment, combining the power of both associative memory custom ASICs and modern Field Programmable Gate Array (FPGA) devices. The mezzanine uses the latest available associative memory devices (AM06) and the most modern Xilinx Ultrascale FPGAs. The results of the test for a complete tower comprising about 0.5 million patterns is presented, using as simulated input events traversing the upgraded CMS detector. The paper shows the performance of the pattern matching, track finding and track fitting, along with the latency and processing time needed. The pT resolution over pT of the muons measured using the reconstruction algorithm is at the order of 1% in the range 3-100 GeV/c.

A 3.9 ps Time-Interval RMS Precision Time-to-Digital Converter Using a Dual-Sampling Method in an UltraScale FPGA

Field programmable gate arrays (FPGAs) manufactured with more advanced processing technology have faster carry chains and smaller delay elements, which are favorable for the design of tapped delay line (TDL)-style time-to-digital converters (TDCs) in FPGA. However, new challenges are posed in using them to implement TDCs with a high time precision. In this paper, we propose a bin realignment method and a dual-sampling method for TDC implementation in a Xilinx UltraScale FPGA. The former realigns the disordered time delay taps so that the TDC precision can approach the limit of its delay granularity, while the latter doubles the number of taps in the delay line so that the TDC precision beyond the cell delay limitation can be expected. Two TDC channels were implemented in a Kintex UltraScale FPGA, and the effectiveness of the new methods was evaluated. For fixed time intervals in the range from 0 to 440 ns, the average RMS precision measured by the two TDC channels reaches 5.8 ps using the bin realignment, and it further improves to 3.9 ps by using the dual-sampling method. The time precision has a 5.6% variation in the measured temperature range. Every part of the TDC, including dual-sampling, encoding, and on-line calibration, could run at a 500 MHz clock frequency. The system measurement dead time is only 4 ns.

A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA

The common solution for a field programmable gate array (FPGA)-based time-to-digital converter (TDC) is constructing a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of the delay elements of TDL determine the TDC time resolution. In this paper, we propose a dual-sampling TDL architecture and a bin decimation method that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve a high time resolution beyond the intrinsic cell delay. Two identical full hardware-based TDCs were implemented in a Xilinx UltraScale FPGA for performance evaluation. For fixed time intervals in the range from 0 to 440 ns, the average time-interval RMS resolution is measured by the two TDCs with 4.2 ps, thus the timestamp resolution of single TDC is derived as 2.97 ps. The maximum hit rate of the TDC is as high as half the system clock rate of FPGA, namely 250 MHz in our demo prototype. Because the conventional online bin-by-bin calibration is not needed, the implementation of the proposed TDC is straightforward and relatively resource-saving.