Abstract
This article discusses the challenges posed on the field-programmable gate array (FPGA) transceivers in terms of phase-determinism requirements for timing distribution at the Large Hadron Collider (LHC) experiments. Having a fixed phase after startups is a major requirement, and the typical phase variations observed in the order of tens of picoseconds after startups while using the state-of-the-art design techniques are no longer sufficient. Each limitation observed in the transmitter and receiver paths of the high-speed transceivers embedded in the Xilinx Ultrascale FPGA family is further investigated and solutions are proposed. Tests in hardware using Xilinx FPGA evaluation boards are presented. In addition to a higher phase determinism, the techniques presented make it possible to fine-tune the skew of a link with a picosecond resolution, greatly simplifying clock-domain crossing inside the FPGAs and providing better short-term stability for the FPGA-recovered clock in a high-speed link.
Highlights
I N THE Large Hadron Collider (LHC), a timing signal derived from the radio frequency driving the particle beams is transmitted to the four LHC experiments, allowing them to be synchronized to the particle bunches circulating in the accelerator rings [1]
New techniques for implementing picosecond-precise transmission using the transceivers embedded in the Xilinx Ultrascale field-programmable gate array (FPGA) family have been demonstrated and characterized in this article
The proposed techniques reach picosecond resolution, which is an improvement over the prior art of one order of magnitude
Summary
I N THE Large Hadron Collider (LHC), a timing signal derived from the radio frequency driving the particle beams is transmitted to the four LHC experiments, allowing them to be synchronized to the particle bunches circulating in the accelerator rings [1]. From an operational point-of-view, it is highly desirable to avoid performing such a calibration every time a node in the system needs to be restarted as this could create chaotic operating conditions This leads to a major requirement of a timing distribution system at the LHC experiments: the relative time offsets between different nodes shall not change across multiple system restarts/initializations. In the LHC phase-1 upgrades (2019-2020), the Large Hadron Collider Beauty (LHCb) experiment and A Large Ion Collider Experiment (ALICE) are undertaking a major upgrade of their TTC system by replacing the legacy TTC circuits Both experiments use FPGA-based boards in the back end to transmit the TTC signals to a new radiation-hard custom-made ASIC, the GigaBitTransceiver (GBTx) [3]. The measurements carried out do not allow to distinguish phase variations of the order of picoseconds due to their low resolution
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