Ultra-low Off Research Articles

All-2D-Materials Subthreshold-Free Field-Effect Transistor with Near-Ideal Switching Slope.

The Boltzmann Tyranny, set by thermionic statistics, dictates the lower limit of switching slope (SS) of a MOSFET to be 60 mV/dec, the fundamental barrier for low-dissipative electronics. The large SS leads to nonscalable voltage, significant leakage, and power consumption, particularly at short channels, making transistor scaling an intimidating challenge. In recent decades, an array of steep-slope transistors has been proposed; none is close to an ideal switch with ultimately abrupt switching (SS ∼ 0 mV/dec) between the binary logic states. We demonstrated an all-2D-materials van-der-Waals-heterostructure (vdW)-based FET that exhibits ultrasteep switching (0.33 mV/dec), a large on/off current ratio (∼107), and an ultralow off current (∼0.1 pA). The "Subthreshold-Free" operation achieved by the collective behavior of functional materials enables FET switching directly from the OFF-state to the ON-state with entirely eliminated subthreshold region, behaving as the ideal logic switch. Two-inch wafer-scale device fabrication is demonstrated. Boosted by device innovation and emerging materials, the research presents an advancement in achieving the "beyond-Boltzmann" transistors, overcoming one of the CMOS electronics' most infamous technology barriers that have plagued the research community for decades.

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors

Abstract3D NAND has been enabling continuous NAND density and cost scaling beyond conventional 2D NAND since sub‐20‐nm nodes. However, its poly‐Si channel suffers from low mobility, instability caused by grain boundaries, and large device‐to‐device variations in electrical characteristics at highly scaled device dimensions. These drawbacks can be overcome by introducing an amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) channel, which has the advantages of ultralow OFF current, back‐end‐of‐line compatibility, higher mobility than poly‐Si, and free of grain boundaries due to the amorphous nature. In this work, ultrascaled floating‐gate (FG) transistors with a channel length down to 60 nm are reported, achieving the highest ON current of 127 µA µm−1 among all reported a‐IGZO‐based flash devices for high‐density, low‐power, and high‐performance 3D NAND applications. Furthermore, a nonvolatile and area‐efficient ternary content‐addressable memory (TCAM) with only two parallel‐connected a‐IGZO FG transistors is experimentally demonstrated to address the TCAM scalability issue. Experimentally calibrated array‐level simulations show that this design achieves at least a 240 × array‐size scalability and a 2.7‐fold reduction in search energy than TCAMs based on complementary metal‐oxide‐semiconductor technology using 16 transistors, two‐transistor‐two‐resistive random access memory, and two‐ferroelectric field‐effect‐transistor.

Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process

Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

High sensitive and stable self-powered solar-blind photodetector based on solution-processed all inorganic CuMO2/Ga2O3 pn heterojunction

Solar-blind photodetection systems, which can convert solar-blind deep ultraviolet light into an electrical signal, have been designed for practical use owing to their high sensitivity and accuracy. As one of the most suitable semiconductors for solar-blind photodetection, β-Ga2O3 can construct a pn type photodetector with another semiconductor material to meet the demands of energy savings, miniaturization and high efficiency. As a kind of natural p-type material, delafossite semiconductor materials CuMO2 (M = Al3+, Ga3+, In3+, Cr3+) have attracted much attention recently. The band alignment of CuMO2 is staggered with that of n-type β-Ga2O3; hence, the photogenerated electrons and holes tend to transfer through the interface in the opposite directions, resulting in spatial separation of charge carriers. Meanwhile, the fast hole diffusion coefficient (10−2–101 cm2 V−1 s−1) of CuMO2 guarantees the transport of holes, which is difficult in β-Ga2O3 owing to its intrinsic electronic structure. More importantly, compared with the widely used p-type materials, CuMO2 materials are almost insensitive to UVA light owing to the forbidden intrinsic direct transitions between the conduction and valence bands. Hence, the CuMO2/β-Ga2O3 pn junction photodetector exhibits high sensitivity, and the working spectral region is not extended to the UVA region. In this study, n-β-Ga2O3/p-CuMO2 (M: Ga3+, Cr3+) pn junction photodetectors were prepared by a simple solution process method. Due to the high crystallinity of the as-grown CuGaO2 and CuCrO2, the CuGaO2/β-Ga2O3 and CuCrO2/β-Ga2O3 pn junction photodetectors demonstrate an ultralow off state current of 51/61 fA, a superhigh on-to-off state current ratio of 2.3 × 104/3.5 × 104 and a high rejection ratio (R254/R365) of 2 × 104/2.8 × 104 under a bias of 0 V. The CuMO2/β-Ga2O3 pn junction photodetector satisfies the requirements of high sensitivity, stable and energy saving and has wide practical application prospect in solar-blind detection systems.

Unidirectional Threshold Switching Induced by Cu Migration with High Selectivity and Ultralow OFF Current under Gradual Electroforming Treatment

A gradual electroforming process was implemented on the pristine Pt/HfOx/Cu/Pt structure to realize volatile threshold switching characteristics of a diffusive memristor. The reported devices exhib...

Nanoscale 3D Stackable Ag-Doped HfOx-Based Selector Devices Fabricated through Low-Temperature Hydrogen Annealing.

Electrochemical metallization-based threshold switching devices with active metal electrodes have been studied as a selector for high-density resistive random access memory (RRAM) technology in crossbar array architectures. However, these devices are not suitable for integration with three-dimensional (3D) crossbar RRAM arrays due to the difficulty in vertical stacking and/or scaling into the nanometer regime as well as the asymmetric threshold switching behavior and large variation in the operating voltage. Here, we demonstrate bidirectional symmetric threshold switching behaviors from a simple Pt/Ag-doped HfOx/Pt structure. While fabricating the Pt/Ag-doped HfOx/Pt film using a 250 nm hole structure, filaments composed of Ag nanoclusters were constructed through a low-temperature (∼200 °C) hydrogen annealing process where the shape of the film in a nanoscale via a hole structure was maintained for integration with 3D stackable crossbar RRAM arrays. Finite Ag filament paths in the HfOx layer led to uniform device-to-device performances. Moreover, we observed that the hydrogen annealing process reduced the delay time through the reduction of the oxygen vacancies in the HfOx layer. Consequently, the proposed Pt/Ag-doped HfOx/Pt-based nanoscale selector devices exhibited excellent performance of high selectivity (∼105), ultralow OFF current (∼10 pA), steep turn-on slope (∼2 mV/decade), and short delay time (3 μs).

Directed Assembly of Nanoparticle Threshold‐Selector Arrays

AbstractThe directed assembly of ordered arrays of cubic silver nanoparticles featuring distinct electrical threshold‐switching characteristics is reported. Threshold selectors are key elements for nonvolatile resistive random‐access‐memory architectures, as they suppress sneak path currents in crosspoint arrays. Nanocubes are site‐selectively immobilized on a TiO2‐coated silicon surface via a complementary molecular surface functionalization of nanoparticles and substrate based on a Cu(I)‐catalyzed alkyne‐azide cycloaddition without any physical template. Electrical characterization of individual silver nanocubes by conductive‐probe atomic force microscopy reveals pronounced and reproducible threshold‐switching behavior, featuring ultralow OFF currents below 1 pA, steep turn‐on slopes of <50 mV dec−1 and ON‐OFF ratios in excess of 103. Numerical simulation of Ag‐ion migration dynamics in the TiO2 electrolyte using a kinetic Monte Carlo model supports a switching mechanism based on conductive filament formation from Ag nanoclusters, and their reversible rupture in the low‐voltage regime. Assembled Ag nanocube threshold selectors are proposed for applications in memristive memory architectures, in particular for future highly integrated 3D circuitry.

A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model

Abstract In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and g m–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.

Dual-Layer Selector With Excellent Performance for Cross-Point Memory Applications

We demonstrate a CuS/GeSe dual-layer selector with excellent performance. This CuS/GeSe dual-layer selector exhibits ultrahigh selectivity ( $\text {1.25}\times \text {10}^{\text {9}}$ ), high on-current drive ( $600~\mu \text{A}$ ), ultralow off current (~100 fA), and extremely steep switching slope (<1.4 mV/dec). This selector shows significant threshold switching behavior by introducing CuS as the ion supply layer to implant limited Cu ions into GeSe layer, to form unstable filaments at high voltage and retract Cu ions at low voltage. In addition, Cu/GeSe devices were fabricated as a comparison, showing desirable memory switching. These two devices are of great potential for cross-point memory applications.

Excellent selector performance in engineered Ag/ZrO2:Ag/Pt structure for high-density bipolar RRAM applications

A high-performance selector with bidirectional threshold switching (TS) characteristics of Ag/ZrO2/Pt structure was prepared by incorporating metallic Ag into the ZrO2 matrix. The bidirectional TS device exhibited excellent switching uniformity, forming-free behavior, ultra-low off current of &amp;lt;1 nA and adjustable selectivity (from 102 to 107). The experiment results confirmed that metallic Ag clusters were penetrated into the ZrO2 matrix during the annealing process, which would function as an effective active source responsible for the bidirectional TS. The volatile behavior could be explained by the self-dissolution of unstable filaments caused by minimization of the interfacial energy and thermal effect. Furthermore, a bipolar-type one selector-one resistor (1S-1R) memory device was successfully fabricated and exhibited significant suppression of the undesired sneak current, indicating the great potential as selector in a cross-point array.

High-Performance Silicon Nanotube Tunneling FET for Ultralow-Power Logic Applications

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs.

Resist-assisted assembly of single-walled carbon nanotube devices with nanoscale precision

We report a novel resist-assisted dielectrophoresis method for single-walled carbon nanotube (SWCNT) assembly. It provides nanoscale control of the location, density, orientation and shape of individual SWCNTs. Sub-50nm accuracy and a yield higher than 85% have been achieved. Using the method, we demonstrate suspended-body SWCNT field-effect transistors (FETs) with back-gate and sub-100nm air-gap lateral-gate configurations. The suspended-body SWCNT FETs show excellent electrical characteristics with Ion/Ioff∼107, ultra-low off currents ∼10−14A and small subthreshold swings. The technique contributes to the ultimate solution for bottom-up fabrication of a broad field of CNT-based devices, such as: complementary metal–oxide-semiconductor and nano-electrical–mechanical-system devices for sensing and radio-frequency applications. Moreover, the versatile method could be applied to the assembly of many other promising materials, such as: nanowires and graphene flakes.

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

Ultra-low off current ( I off < 1 pA/μm) “silicon on thin buried oxide (SOTB)” CMOSFETs were developed using 65-nm technology. The off current of SOTB CMOSFETs was studied and gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length. A back-gate bias in a SOTB scheme was demonstrated, and the inverter delay was compared with conventional low-standby-power bulk CMOSFETs. We show small variation in SOTB devices and estimate the standby leakage of a 1-M bit SRAM. The half threshold voltage standard deviation ( σV th) of SOTB devices corresponds to a reduction in the standby leakage current of less than half. The ultra-low off current with a small variation also further reduces the standby leakage.

Spice Modeling of Silicon Nanowire Field-Effect Transistors for High-Speed Analog Integrated Circuits

Vertical nanowire surrounding gate field-effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects and to achieve ultralow off current. This paper presents the fully depleted BSIMSOI modeling of low-power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics, and measuring the capabilities of these transistors for high-speed analog and RF applications. When biased with V ds = 0.5 V and V gs = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 muA and 0.7 muA drain currents, 14 muA/V and 8 muA/V transconductances, 400 kOmega and 1.1 MOmega output resistances, 36 THz and 25 THz unity-current-gain cutoff frequencies, and 120 THz and 100 THz maximum frequency of oscillations, respectively. A single-stage CMOS SGFET amplifier dissipates 1.64 muW power and provides 500 GHz bandwidth with -6.5 gain and -24 dBm third-order intermodulation distortion tones for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. The large-signal operation of the amplifier with 1 V output swing exhibits 2.2 ps delay, 5.4 ps rise time, and 4.7 ps fall time while oscillating at 30 GHz. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next-generation very-large-scale integration (VLSI) technology.

Comparison of N-MOSFET lifetime estimates based on GIDL enhancement and transconductance degradation as criteria : A. B. Joshi and D. L. Kwong. Solid-State Electronics, 35(12), 1757 (1992)

Ultra-low off current (Ioff < 1 pA/μm) “silicon on thin buried oxide (SOTB)” CMOSFETs were developed using 65-nm technology. The off current of SOTB CMOSFETs was studied and gate-induced drain leakage (GIDL) was adequately reduced by controlling the gate-overlap length. A back-gate bias in a SOTB scheme was demonstrated, and the inverter delay was compared with conventional low-standby-power bulk CMOSFETs. We show small variation in SOTB devices and estimate the standby leakage of a 1-M bit SRAM. The half threshold voltage standard deviation (σVth) of SOTB devices corresponds to a reduction in the standby leakage current of less than half. The ultra-low off current with a small variation also further reduces the standby leakage.