Ultrathin Silicon Oxynitride Research Articles

Ultrathin SiONC passivation of c-Si by UHV thermal annealing in O₂/N₂: Chemical composition, morphology, and photoluminescence insights

This study investigates the impact of Ultra-High Vacuum (UHV) Thermal annealing in a N₂/O₂ atmosphere on the passivation of Ar ion etched crystalline silicon (c-Si) surfaces. A comprehensive analysis of the resulting ultrathin Silicon OxyNitride Carbide layer (SiONC) was conducted using X-ray Photoelectron Spectroscopy (XPS), Ultra-Violet Spectroscopy (UPS), Photoluminescence Spectroscopy (PL), and Atomic Force Microscopy (AFM). XPS revealed a significant transformation in chemical composition from a carbon-rich contaminated surface SiO1.02C2.98 to an oxygen- and nitrogen-containing passivated layer SiO0.13N0.10C0.28. UPS measurements elucidated changes in the electronic structure and Fermi level position at the c-Si/SiONC interface. AFM imaging demonstrated the formation of non-uniform SiONC islands, influencing surface morphology. Notably, PL spectroscopy indicated enhanced orange and red luminescence with energies of 2.0 and 1.73 eV, respectively, attributed to the SiONC layer. The enhanced luminescence, coupled with improved thermal stability and oxidation resistance, positions the SiONC layer as a promising material for advancing the performance of silicon-based optoelectronic devices, such as solar cells and light-emitting diodes (LEDs). This study provides fundamental insights into the correlation between the chemical, electronic, and morphological properties of the SiONC layer and its potential for improving c-Si device performance.

N-type polysilicon passivating contacts using ultra-thin PECVD silicon oxynitrides as the interfacial layer

We describe the optimization of an ultra-thin silicon oxynitride (SiOxNy) layer deposited by plasma enhanced chemical vapor deposition (PECVD) as an interfacial layer for phosphorus doped polysilicon (poly-Si) passivating contacts. Our results demonstrate the possibility of depositing the thin interfacial layer and the intrinsic amorphous silicon (a-Si) film in a single PECVD process. We found that the gas flow rates strongly influence the properties of the SiOxNy layers, such as the refractive indices, chemical bond compositions and structural stabilities, which significantly affect the properties of the resulting polysilicon passivating contact structures. The passivation quality initially increased and then decreased with a decreasing N2O/SiH4 flow ratio, in the gas flow range of uniform deposition, while the contact resistivity decreased significantly. We found an optimal gas flow ratio of N2O:SiH4:N2 = 25:9:361, with which we obtained uniform polysilicon passivating contacts with a high implied open-circuit voltage (iVoc) of 711 mV and a low contact resistivity ρc of 6.6 mΩ cm2.

NrGO Floating Gate/SiOXNY Tunneling Layer Stack for Nonvolatile Flash Memory Applications

This paper presents an ultra–thin silicon oxynitride (SiOXNY, 4 nm) tunneling layer, nitrogen functionalized reduced graphene oxide (NrGO, 3–5 layer) floating gate (FG) and poly (methyl methacrylate) (PMMA, 60 nm) blocking layers based Al/PMMA/NrGO/SiOXNY/p–Si/Au, non–volatile flash memory (NVFM) structures. The ultra–thin SiOXNYhelps in improving the interface with Si, resulting in lower gate leakage current density and considerable enhanced retention characteristics. The nitrogen engineered GO followed by reduction to NrGO under UV illumination attributes to the modification of the physiochemical properties, hence beneficial for non-volatile memory applications. The uniform, stress free and low temperature processing advocates the potential of PMMA as blocking layer for improved memory characteristics. The electrical characterizations on the fabricated Al/PMMA/NrGO/SiOXNY/p–Si/Au gate stack demonstrates a memory window ( ${\delta }\text{W}$ ) of ~1.25 V @ ± 3 V and ~2.6 V @ ± 5 V, low gate leakage current density (J) ~10 nA/cm2@ −1 V, retention $\sim 3 \times 10^{11}$ sec (> 10 years with extrapolation) and endurance of more than 100 cycles.

Alternate lanthanum oxide/silicon oxynitride-based gate stack performance enhancement due to ultrathin oxynitride interfacial layer for CMOS applications

Metal–insulator–semiconductor (MIS)-based Pt/La2O3/SiOXNY/p-Si/Pt structures are fabricated using ultrathin silicon oxynitride (SiOXNY ~ 4 nm) interfacial layer underneath of lanthanum (III) oxide (La2O3 ~ 7.8 nm) with Pt as gate electrode for CMOS applications. Capacitance–voltage (C–V) characteristics of Pt/La2O3/SiOXNY/p-Si/Pt at 500 kHz showed a positive gate bias threshold voltage (Vth) shift of ~ 0.43 V (~ 43.8%) and flat-band (Vfb) shift of ~ 1.24 V (~ 42.3%) as compared to Pt/La2O3/p-Si/Pt MIS structures, attributing to the reduction in effective positive oxide charges at La2O3/SiOXNY/Si gate stack. Likewise, conductance–voltage (G–V) characteristics show ~ 0.56 (~ 44.4%) reduction in FWHM for Pt/La2O3/SiOXNY/p-Si/Pt as compared to Pt/La2O3/p-Si/Pt MIS structures revealing the reduction in interface states at La2O3/SiOXNY/Si interface. There is a considerable reduction of effective oxide charge concentration (Neff) ~ 3.99 × 1010 cm−2 by (~ 15.2%) and ~ 56.8% lower gate leakage current density ~ 4.47 × 10−7 A/cm2 (|J|–V) at − 1 V for SiOXNY based MIS structures w.r.t its counterpart. Capacitance–time (C–t) characteristics, constant voltage stress (CVS) and temperature measurements for C–V and |J|–V demonstrate the considerable retention ~ 12 years, electrical improvement and reliability of MIS structures. The depth profile analysis X-ray photoelectron spectroscopy (XPS) for SiOXNY/Si gate stack clearly reveals that less nitrogen concentration in bulk than SiOXNY/Si interface. Atomic force microscopy (AFM) micrographs of La2O3/Si and SiOXNY/Si showed the significantly lesser r.m.s roughness of ~ 1.11 ± 0.39 nm and ~ 0.97 ± 0.11 nm, respectively. Thus, the ultrathin SiOXNY interfacial layer underneath of La2O3 demonstrates a significantly improved electrical performance and prelude the gate stack strong potential for reliable CMOS logic devices and integrated circuits.

Structural and Electrical Characteristics of Oxygen Annealed ALD-ZrO2/SiON Gate Stack for Advanced CMOS Devices

Keeping in view the potential demands of 22 nm (and beyond) technology nodes for high-k dielectric materials, the device reliability was taken into consideration by selecting appropriate atomic scale deposition techniques and device characterization methods. This paper presents the fabrication of n-Si/ALD-ZrO2 gate stack with an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL). The problem of the gate leakage current has been resolved by post deposition annealing (PDA) of ZrO2 film ~ 11.63 nm in oxygen ambient on the silicon substrate followed by the pre-growth of SiON IL ~ 6.92 nm. The structural, morphological and film thickness studies have been performed by the characterization techniques such as XRD, AFM and FESEM respectively. Electrical characterizations such as capacitance-voltage (C-V) and current density-voltage (J-V) reveal the improved results for O2 annealed ZrO2 sample relative to the as-deposited ZrO2 sample in terms of suppressed gate leakage current (~2.8 ×10-8 A/cm2), increased dielectric constant (~ 33) and reduced effective oxide thickness (EOT~ 1.37 nm). O2 annealed ZrO2/SiON gate stack exhibits excellent results in terms of reduced EOT, reduced leakage current and increased dielectric constant relative to as-deposited ZrO2/SiON gate stack.

Structural and Electrical Characteristics of Oxygen Annealed ALD-ZrO2/Sion Gate Stack for Advanced CMOS Devices

Keeping in view the potential demands of 22 nm (and beyond) technology nodes for high-k dielectric materials, the device reliability was taken into consideration by selecting appropriate atomic scale deposition techniques and device characterization methods. This paper presents the fabrication of n-Si/ALD-ZrO2 gate stack with an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL). The problem of the gate leakage current has been resolved by post deposition annealing (PDA) of ZrO2 film ~ 11.63 nm in oxygen ambient on the silicon substrate followed by the pre-growth of SiON IL ~ 6.92 nm. The structural, morphological and film thickness studies have been performed by the characterization techniques such as XRD, AFM and FESEM respectively. Electrical characterizations such as capacitance-voltage (C-V) and current density-voltage (J-V) reveal the improved results for O2 annealed ZrO2 sample relative to the as-deposited ZrO2 sample in terms of suppressed gate leakage current (~ 2.8 × 10-8 A/cm2), increased dielectric constant (~ 33) and reduced effective oxide thickness (EOT~ 1.37 nm). Furthermore, in this paper, we will present comparative studies on types of gate stacks viz. HfO2/SiO2 , HfO2/SiON, Ar-annealed ZrO2/SiON, N2 annealed ZrO2/SiON and O2 annealed ZrO2/SiON and their comparative analysis indicates better results for O2 annealed ZrO2/SiON in terms of reduced EOT, reduced leakage current and increased dielectric constant. Figure 1

Argon Annealed ALD-ZrO2/SiON Gate Stack for Advanced CMOS Devices

We report on the fabrication of ultra-thin silicon oxynitride (SiON ~ 5.34 nm) as sacrificial layer (SL) for n-Si/ALD-ZrO2 gate stack followed by the post deposition annealing (PDA) of ZrO2 in argon ambient. The surface morphological studies include atomic force microscopy (AFM) and field emission scanning electron microscopy (FESEM) whereas the thicknesses of the grown films were confirmed by both ellipsometry and FESEM cross-sectional studies. The surface topographical study suggests the r.m.s. roughness of 0.796 nm for nano zirconia film after rapid thermal annealing (RTA). Electrical parameters such as dielectric constant (K), effective oxide thickness (EOT), leakage current density (J), effective oxide charge (Qeff) and series resistance (Rs) were extracted through C-V and I-V measurements and the determined values of K, J, EOT, Qeff and Rs at 100 KHz are 26, 8.75 × 10-9 A/cm2, 2.1 nm, 0.42 × 1013 cm-2 and 4.54 KΩ respectively. The concept of SiON SL has significantly suppressed the existing unacceptable gate leakage current and the interfacial traps owing to appropriate segregation of nitrogen at the interface of SiON/ZrO2. Moreover, PDA of ZrO2 film in argon ambient at 5000 C has reduced the r.m.s. roughness and also contributed to the overall reduction of gate leakage current density, thereby, making ALD-ZrO2/SiON gate stack quite attractive for advanced CMOS devices.

Argon Annealed ALD-ZrO2/SiON Gate Stack for Advanced CMOS Devices

Now-a-days, high-k dielectric materials are in demand as they not only inhibit direct tunneling but also ensures relatively thicker oxides. To replace SiO2 as gate dielectric, a number of high-k materials have been extensively studied such as aluminum oxide (Al2O3), zirconium dioxide (ZrO2), cerium oxide (CeO2), hafnium oxide (HfO2) and titanium dioxide (TiO2). Among them, ZrO2 is one of the most outstanding candidates due to its excellent chemical, physical and electrical properties such as good thermodynamic stability with silicon, high dielectric constant, high melting point, high refractive index, and sufficient band gap. Atomic layer deposition (ALD) method having the benefit of low temperature deposition and extremely precise thickness control has been utilized for the deposition of ZrO2 film. Additionally, the post deposition annealing (PDA) of ZrO2in argon (Ar) ambient has been performed along with Ti-Pt as bilayer metal gate. Taking into consideration the state-of-the-art research progress, we report the fabrication of ultra-thin silicon oxynitride (SiON) as a sacrificial layer (SL) for n-Si/ALD-ZrO2 gate stackfollowed by post deposition annealing (PDA) of ZrO2 in argon (Ar) ambient. The surface roughness for the Ar annealed ZrO2 film measured using atomic force microscopy (AFM) was found to be 0.796 nm whereas the thicknesses of SiON SL ~ 5.34 nm and ZrO2 film ~ 11.63 nm were corroborated by field emission scanning electron microscope (FESEM) and spectroscopic ellipsometer (SE). Electrical characterizations such as capacitance voltage and current voltage measurements indicates the improved results for n-Si/ALD-ZrO2/Ti-Pt MOS capacitor in terms of various performance parameters such as dielectric constant (K), effective oxide thickness (EOT), leakage current density (J), effective oxide charge (Qeff) and series resistance (Rs) and their determined values are 26, 2.1 nm, 8.75 × 10-9 A/cm2, 0.42 × 1013 cm-2 and 4.54 KΩ respectively. The noble concept of SiON SL along with the PDA of ZrO2 in Ar ambient can enable the further scaling of n-Si/SiON/ZrO2 gate stack without the adverse effects of gate leakage current. Some of the important results obtained from the reported work have been exemplified in the figures below. Figure 1

Structural and electrical characteristics of ALD-HfO2/n-Si gate stack with SiON interfacial layer for advanced CMOS technology

We report the fabrication of an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL) for n-Si/ALD-HfO2 gate stack with reduced leakage current. The XRD, AFM, FTIR, FESEM and EDAX characterizations have been performed for structural and morphological studies. Electrical parameters such as dielectric constant (K), interface trap density (Dit), leakage current density (J), effective oxide charge (Qeff), barrier height (Φbo), ideality factor (ƞ), breakdown-voltage (Vbr) and series resistance (Rs) were extracted through C-V, G-V and I-V measurements. The determined values of K, Dit, J, Qeff, Φbo, ƞ, Vbr and Rs are 14.4, 0.5 × 10 11 eV−1 cm−2, 2.2 × 10−9 A/cm2, 0.3 × 1013 cm−2, 0.42, 2.1, −0.33 and 14.5 MΩ respectively. SiON growth prior to HfO2 deposition has curtailed the problem of high leakage current density and interfacial traps due to sufficient amount of N2 incorporated at the interface.

Physical characterization of ultrathin silicon oxynitrides grown by Rapid Thermal Processing aiming to MOS tunnel devices

Oxynitrides were grown in a homemade Rapid Thermal Processor (RTP) using a low mass quartz carrier, to obtain thin oxynitrides over large areas of 3 inches silicon p-type wafers. Layers with thickness varying from 0.97 to 2.39 nm with uniformity better than 0.4%, were obtained at 700 and 850°C, in a mixed ambient of nitrogen and oxygen (4N2:3O2 in volume). The nitrogen concentration was obtained with the aid of X-ray photoelectron spectroscopy (XPS) and was 0.6 at%. On the other hand, the Si/O ratio in the oxynitride was approximately 1.9, indicating an almost stoichiometric SiO2 with a small amount of nitrogen. In addition, using the 16O(α, α) elastic-scattering signal at 3.039MeV, the planar concentration of oxygen was 5.5×1015cm2 for the oxynitride grown at 850°C during 40s.

Growth of silicon oxynitride films by atmospheric pressure plasma jet

Ultra-thin silicon oxynitride (SiOxNy) layers were deposited by direct interaction of plasma species formed in an atmospheric pressure plasma jet (APPJ) with a silicon wafer. APPJs have been ignited in mixtures of helium (He) together with several nitrogen-based compounds. The chemical composition of the APPJ treated silicon surfaces was analysed by ultra-high vacuum x-ray photoelectron spectroscopy (XPS). The obtained N 1s XPS spectra showed that even 5 min of APPJ treatment is sufficient to fabricate SiOxNy films with a few nanometre thickness. A Si substrate exposed to an APPJ generated in a mixture of He/NH3 resulted in the most efficient growth of SiOxNy films, indicated by the strongest N 1s XPS signal among all studied gas mixtures. Moreover, the N 1s spectra exhibited two major characteristics of chemical bonding structures attributed to nitrogen bonded to three silicon surface atoms, N–(S)3, and nitrogen bonded to two silicon surface atoms and one oxygen atom, (Si)2–N–O.

Nitroxidation of H-Terminated Si(111) Surfaces with Nitrobenzene and Nitrosobenzene

Ultrathin silicon oxynitride films have attracted substantial attention as gate dielectrics. In this work, we investigate a wet-chemistry approach to introduce a monolayer silicon oxynitride film by reacting H-terminated Si(111) surface with nitro- or nitrosobenzene. The bifunctional aromatic molecules serve as a source of oxygen and nitrogen, while phenyl ring remains intact after the reaction and can be used for further modifications or as a resist. Fourier-transform infrared (FTIR) spectroscopy and X-ray photoelectron spectroscopy (XPS) were used to confirm surface reaction and to quantify surface coverage. Density functional theory (DFT) cluster calculations were employed to explore feasible reaction pathways, predict the vibrational spectra of possible reaction products, and compare the observed XPS binding energies with calculated N 1s core level energies. Substantial differences in reactions of these two molecules on silicon provide the opportunity to tune the nitroxidation process to achieve the d...

Resilience of ultra-thin oxynitride films to percolative wear-out and reliability implications for high-κ stacks at low voltage stress

Localized progressive wear-out and degradation of ultra-thin dielectrics around the oxygen vacancy percolation path formed during accelerated time dependent dielectric breakdown tests is a well-known phenomenon documented for silicon oxynitride (SiON) based gate stacks in metal oxide semiconductor field effect transistors. This progressive or post breakdown stage involves an initial phase characterized by “digital” random telegraph noise fluctuations followed by the wear-out of the percolation path, which results in an “analog” increase in the leakage current, culminating in a thermal runaway and hard breakdown. The relative contribution of the digital and analog phases of degradation at very low voltage stress in ultra-thin SiON (16 Å´) is yet to be fully investigated, which represents the core of this study. We investigate the wear-out process by combining electrical and physical analysis evidences with modeling and simulation results using Kinetic Monte Carlo defect generation and multi-phonon trap assisted tunneling (PTAT) models. We show that the transition from the digital to the analog regime is governed by a critical voltage (VCRIT), which determines the reliability margin in the post breakdown phase. Our results have a significant impact on the post-breakdown operational reliability of SiON and advanced high-κ–SiOx interfacial layer gate stacks, wherein the SiOx layer seems to be the weakest link for percolation event.

Reliability issues of double gate dielectric stacks based on hafnium dioxide (HfO 2) layers for non-volatile semiconductor memory (NVSM) applications

In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiO x N y ) as the pedestal layer and hafnium dioxide layer (HfO 2) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of current–voltage characteristics, as well as applying dc stresses in constant current (CCS) and voltage (CVS) mode. Presented results have shown that the application of ultra-thin PECVD silicon oxynitride layer results in significant increase of breakdown voltage value in comparison to MIS structure with only hafnia as the gate dielectric. Moreover, due to the high temperature annealing of deposited SiO x N y layers, MIS device demonstrates much lower leakage currents, as well as higher breakdown voltage values in comparison to device with ‘as-deposited’ SiO x N y bottom layer. The results also proved larger immunity to dc stresses and better retention characteristics of MIS devices with ‘annealed’ oxynitride, in comparison to ‘as-deposited’ pedestal layer.

Effect of Incorporated Nitrogen on the Band Alignment of Ultrathin Silicon-oxynitride Films as a Function of the Plasma Nitridation Conditions

Effect of Incorporated Nitrogen on the Band Alignment of Ultrathin Silicon-oxynitride Films as a Function of the Plasma Nitridation Conditions

Chemical bonding structures of silicon oxynitride films grown by ionised N2 and pure O2 gas mixtures at low temperature

The ultrathin silicon oxynitride (SiOxNy) films were formed using the direct oxynitridation of Si using ionised N2 and pure O2 gas mixtures at the relatively low temperature (600°C). The in situ X‐ray photoelectron spectroscopy (XPS) was used to assess the chemical composition and chemical state of the SiOxNy films. N 1s XPS spectra reveals that at least three characteristic N bonding states such as N≡Si3, N–(SiOx)3 and N = Si2–O bonds are formed in the SiOxNy films. As growth time increases, the N–(SiOx)3 bond is dominant in SiOxNy films, although N≡Si3 bonds are mainly formed in the initial growth stage at the temperature of 600°C. As considering the absence of direct bonding between N and O atoms, the nitridation and oxidation processes are believed to proceed independently. The increase in the growth temperature leads to the breakdown of both N–(SiOx)3 and N≡ = Si3 bonds and transformation into N = Si2–O bonding structure.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

By measuring the minimum supply voltage for normal operation of test random access memories, we detected low-density extrinsic defects in silicon-oxynitride (SiON) gate insulators that were formed by state-of-the-art technologies. The density of the detected defects had a strong correlation with optical thickness dopt, which was ellipsometrically measured, regardless of the processing conditions of the SiON films. We propose to maintain the dopt above a threshold value of 1.7 nm to suppress the problems caused by the defects. The optimization of post nitridation annealing (PNA) condition is promising for meeting the criterion without sacrificing device performance. By elaborate investigations based on the Clausius–Mosotti relation, we found that the optical thickness of SiON films is approximately proportional to the atomic area density in the films. On the basis of this finding, we developed a model, which is an extension of the conventional analytical cell-based model, to figure out the physical process of the extrinsic-defect formation. The results analyzed using the model revealed that the extrinsic defects are formed in the SiON films in the case when the number of normal cells in a vertical arrangement becomes equal to or smaller than the threshold value of 3 or 4.

Transition of Charge Transfer and Tunneling Effect in Ultrathin Silicon Oxynitride Films

not Available.

Nonvolatile Poly-silicon Memory Device with Oxide-Nitride-Oxynitride Stack Structure on Glass for Flat Panel Display

This paper explains how non-volatile memory (NVM) devices with an oxide/nitride/oxynitride (ONO) structure on a rough poly-silicon (poly-Si) surface were fabricated and studied using poly-Si thin film transistor (TFT) technology on a glass substrate. When a flat panel display (FPD) such as an organic light emitting diode (OLED) or a liquid crystal device (LCD) displays a static image, the brightness of the panel is altered because of degradation of the driving current. In order to prevent degradation of the driving current, an NVM device can be applied to the compensation circuit for the pixels of a FPD. To fabricate an NVM device on glass, a metal/oxide/nitride/oxynitride/poly-Si (MONOS) structure with an ultra-thin silicon oxynitride (SiOxNy) using nitrous oxide (N2O) plasma as the tunneling layer was used instead of the general methods of oxidation and deposition for ultra-thin silicon dioxide (SiO2). The memory window of a fabricated NVM device which has a MONOS structure with a tunneling layer of ultra-thin SiOxNy at a programming voltage of − 16 V and erasing voltage of + 11 V for a pulse time of 1s is 2.8 V. This is because of programming and erasure of charges in the silicon nitride (SiNx) layer. Because of the properties of NVM device on glass, NVM devices can be used in various FPD.

Gate voltage dependence on hot carrier degradation at an elevated temperature in a device with ultrathin silicon oxynitride

The effects of hot carrier stress (HCS) at elevated temperature on a device with ultrathin silicon oxynitride have been investigated. It was shown that the degradation of the device was more significant at elevated temperature compared with at room temperature. This behavior attributed to more generation of interface states due to an increase in the high-energy tail electrons. By the theory of electron-electron scattering, the threshold voltage shift was the most severe at the condition of VG>VD. However, based on the results of extrapolating the device lifetime, the worst case stress condition under HCS was the VG=VD condition at elevated temperature due to a higher generation rate.