Ultra-thin Chips Research Articles

Precise modulation of the debonding behaviours of ultra-thin wafers by laser-induced hot stamping effect and thermoelastic stress wave for advanced packaging of chips

Abstract Laser debonding technology has been widely used in advanced chip packaging, such as fan-out integration, 2.5D/3D ICs and MEMS devices. Typically, laser debonding of bonded pairs (R/R separation) is typically achieved by completely removing the material from the ablation region within the release material layer at high energy densities. However, this R/R separation method often results in a significant amount of release material and carbonized debris remaining on the surface of the device wafer, severely reducing product yields and cleaning efficiency for ultra-thin device wafers. Here, we propose an interfacial separation strategy based on laser-induced hot stamping effect and thermoelastic stress wave, which enables stress-free separation of wafer bonding pairs at the interface of the release layer and the adhesive layer (R/A separation). By comprehensively analyzing the micro-morphology and material composition of the release material, we elucidate the laser debonding behavior of bonded pairs under different separation modes. Additionally, we have calculated the ablation threshold of the release material in the case of wafer bonding and established the processing window for different separation methods. This work offers a fresh perspective on the development and application of laser debonding technology. The proposed R/A interface separation method is versatile, controllable and highly reliable, and does not leave release materials and carbonized debris on device wafers, demonstrating strong industrial adaptability, which greatly facilitates the application and development of advanced packaging for ultra-thin chips.

Printed Interconnects for Heterogeneous Systems Integration on Flexible Substrates

AbstractHeterogeneous integration on flexible substrates has been explored in recent years to meet the high‐performance and flexible form factors requirements of several emerging applications. Reliable interconnects, in both 2D and 3D layouts, are critical for the effective use of these systems. But it is challenging to employ conventional bonding and interconnect technology due to considerable mismatches in mechanical and thermal properties. For example, the ultra‐thin chips (UTCs) are too fragile to withstand the static or oscillating forces applied during conventional bonding. In this regard, printing of metal tracks on flexible substrates is a promising alternative to access the contact pads on integrated circuits (ICs), as the interconnects on diverse substrates can be realized at room temperature processing using as much materials as needed. Further, it is easier to attain step coverage. Considering the above attractive features, and the challenges associated with conventional bonding techniques, this article focuses on the development of high‐resolution printing interconnects in both 2D and 3D layouts and explores various printing routes available for high density integration. The article also discusses major conventional interposers/interconnects forming methods and their limitations for flexible hybrid electronics along with few examples of printed interconnects to highlight the opportunities for future.

Effects of die top system and trenches on large thin die mechanical robustness

Abstract Power MOSFET dies in the automotive industry are becoming larger (> 5 x 5 mm) and thinner (< 50 µm) to meet high-performance and lifetime requirements. Ensuring the mechanical robustness of these large ultrathin chips is crucial for reliable electronic devices and high-throughput packaging processes. The high aspect ratio and advanced chip designs incorporating trench technology present significant challenges in semiconductor assembly, packaging, and testing. This paper introduces an experimental front-end strategy aimed at strengthening the front side of large ultrathin dies using various die-top systems. Industry-equivalent 50 µm thick dummy power MOSFET dies were fabricated to evaluate the efficacy of different chip designs and materials, such as polyimide, in mitigating fracture risks. Fabrication-induced stresses and warpage in the device layers were measured using a thin-film stress measurement tool. Additionally, the frontside strength of the ultrathin dies was assessed using the three-point bending method, with the resulting data analyzed via two-parameter Weibull distribution plots. Results demonstrated that the deposition of 5 µm polyimide (PI) on the nitride die topside significantly increased die strength from 339 MPa to 760 MPa, with 5 µm PI proving more effective for die strengthening than 10 µm. The interaction between the metal-trench layer and the die was found to be critical to the robustness of ultrathin dies, influenced by the pattern and layout of the trenches. Die-top metallization designs, such as meandering patterns, showed promising improvements in die strength compared to standard designs. A proposed chip layout aims to maximize polyimide coverage for clip-bonded products on the die topside, leveraging its strengthening effect. The study also demonstrated that dummy reference chips can facilitate rapid and straightforward evaluation of extensive design experiments to identify robust chip designs.

Boosting High-Voltage Practical Lithium Metal Batteries with Tailored Additives

HighlightsFGN-182 electrolytes exhibit highly reversible Li plating/stripping with an average Coulombic efficiency reaching up to 99.56% determined from Auerbach’s test.The gas-evolution process of LiNO3 in high-voltage lithium cobalt oxide (LCO) cathodes is revealed by in situ differential electrochemical mass spectrometry.Pouch cells equipped with high-loading LCO (3 mAh cm−2) cathodes, ultrathin Li chips (25 μm), and lean electrolytes (5 g Ah−1) using optimized electrolyte (FGN-182 + 1%HTCN) demonstrate outstanding cycling performance.

High‐Resolution Printing‐Based Vertical Interconnects for Flexible Hybrid Electronics

AbstractFlexible hybrid electronics (FHE) is an emerging area that combines printed electronics and ultra‐thin chip (UTC) technology to deliver high performance needed in applications such as wearables, robotics, and internet‐of‐things etc. The integration of UTCs on flexible substrates and the access to devices on them requires high resolution interconnects, which is a challenging task as thermal and mechanical mismatches do not allow conventional bonding methods to work. To address this challenge, the resource‐efficient, area‐efficient, and low‐cost printing routes for obtaining vertical interconnection accesses (VIAs) are demonstrated here. It is demonstrated how high‐resolution printers (electrohydrodynamic and extrusion‐based direct‐ink writing printers) can be used for patterning of high‐resolution, freeform, vertical conductive structures. To access the transistors on UTCs, the VIAs, obtained using conventional photolithography and plasma etching steps, are filled with conductive silver nanoparticle‐based ink/paste using high‐resolution printers. Comprehensive studies are performed to compare and benchmark in terms of: i) the printing speed and throughput of the printers, ii) the electrical performance of vertically connected transistors in UTCs, and iii) the electrical performance stability of FHE system (interconnects and UTCs) under mechanical bending conditions. This in‐depth study shows the potential use of printing technologies for development of high‐density 3D integrated FHE systems.

Ultrathin Parylene C-based sensitivity-gain nanoplasmonic sensor integrated on VCSEL for Aβ42 detection

As Alzheimer's disease prevalence continues to rise, there is an increasing demand for efficient on-chip biosensors capable of early biomarker detection. This study presents a novel biosensor chip leveraging vertical cavity surface emitting laser (VCSEL) technology, with Parylene C serving as the antibody coupling layer and utilizing a streamlined one-step antibody modification method. Integration of Parylene C enhances chip sensitivity from 34.28 μW/RIU to 40.32 μW/RIU. Moreover, post-testing removal of Parylene C enables chip reusability without significant alteration of results. The sensor demonstrates effective detection of Aβ42, an Alzheimer's biomarker, exhibiting a linear range of 1–200 ng/mL and a detection limit of 0.26 ng/mL. These findings underscore the reusability and reliability of the ultrathin Parylene C-based VCSEL biosensor chip, highlighting its potential for point-of-care Alzheimer's disease diagnosis.

Stacked Chip-Based Terahertz Metamaterials and Their Application

A terahertz (THz) metamaterial design mechanism based on a stacked chip is proposed. Unlike the traditional sandwich-type metamaterial design mechanism based on the “resonant layer–dielectric layer–ground layer” structure, it adopts a stacked design of upper and lower metamaterial chips to achieve a new structure based on the “dielectric layer–resonant layer–air layer–ground layer” structure. This could break through the thickness limitations and construct an ultra-thin metamaterial upper chip. To verify the effectiveness of this method, we applied it to the field of THz perfect absorbers. We designed, simulated, and prepared a terahertz stacked chip-based perfect absorber with an upper-chip thickness less than 1/800 of the wavelength. Then, a reflective spectroscopy system based on a vector network analyzer is built to test the absorption performance. The measured results show that it has an absorptivity of 98.4% at 0.222 THz, which is in good agreement with simulations.

Flexible Tactile Sensors Using AlN and MOSFETs Based Ultra-Thin Chips

This paper presents ultrathin chips (UTCs) based flexible tactile sensing system for dynamic contact pressure measurement. The device comprises of an AlN piezocapacitor based UTCs tightly coupled with another UTCs having metal-oxide-semiconductor field-effect transistors (MOSFETs). In this arrangement the AlN piezocapacitor forms the extended gate of MOSFETs. Both AlN piezocapacitor and MOSFET based UTCs are obtained by post-process reduction of wafer thicknesses to ~35μm using backside lapping. The performances of both UTCs were evaluated both before and after thinning and there was no noticeable performance degradation. The UTC-based AlN piezocapacitor exhibited six times higher sensitivity (43.79mV/N) than the thin filmbased AlN sensors. When coupled with MOSFETs based UTC, the observed sensitivity was 0.43N-1. The excellent performance, flexible form factor and compactness shows the potential of presented device in applications such minimal invasive surgical instruments where high-resolution tactile feedback is much needed.

Thin‐Film Transistors for Integrated Circuits: Fundamentals and Recent Progress

AbstractHigh‐performance thin‐film transistors (TFTs) integrated circuits (ICs) have become increasingly necessary to meet the emerging demands such as healthcare, edge computing, and the Internet of Things, etc. This article aims to point out the potential development trends and bottlenecks of TFT ICs, enhancing their performance in terms of electronic performance, stability, consistency, CMOS design, and manufacturing capability. Basic device structures and overall metrics of TFT ICs are explored, as well as their superiority compared to silicon‐based ultrathin chips. Hydrogenated amorphous silicon, low‐temperature polycrystalline silicon, and amorphous oxide semiconductors are widely used in displays due to their ability to be deposited on large areas at low processing temperatures and low cost, and are validated in many prototypes for TFT ICs. Their conduction mechanisms, process flows, performance evaluation, and recent advances are comprehensively viewed. In addition, the potential of emerging low‐dimensional materials as next‐generation channel materials is discussed, along with their limitations and progress in this field. Finally, the major challenges in manufacturing high‐performance TFT ICs and future perspectives are summarized.

Coupled Excitation Strategy for Crack Initiation at the Adhesive Interface of Large-Sized Ultra-Thin Chips

The initial excitation of interface crack of large-size ultra-thin chips is one of the most complicated technical challenges. To address this issue, the reversible fracture characteristics of a silicon-based chip (chip size: 1.025 mm × 0.4 mm × 0.15 mm) adhesive layer interface was examined by scanning electron microscope (SEM) tests, and the characteristics of a cohesive zone model (CZM) unit were obtained through peel testing. The fitting curve of the elastic bilinear model was in high agreement with the experimental data, with a correlation coefficient of 0.98. The maximum energy release rate required for stripping was GC = 10.3567 N/m. Subsequently, a cohesive mechanical model of large-size ultra-thin chip peeling was established, and the mechanical characteristics of crack initial excitation were analyzed. The findings revealed that the larger deflection peeling angle in the peeling process resulted in a smaller peeling force and energy release rate (ERR), which made the initial crack formation difficult. To mitigate this, a coupling control method of structure and force surface was proposed. In this method, through structural coupling, the change in chip deflection was greatly reduced through the surface coupling force, and the peeling angle was greatly improved. It changed the local stiffness of the laminated structure, made the action point of fracture force migrate from the center of the chip to near the edge of the chip, the peeling angle was increased, and the energy release rate was locally improved. Finally, combined with mechanical analysis and numerical simulation of the peeling process, the mechanical characteristics of peeling were analyzed in detail. The results indicated that during the initial crack germination process, the ERR of the peel interface is significantly increased, the maximum stress value borne by the chip is significantly reduced, and the peel safety and reliability are greatly improved.

Flip chip bonding on stretchable printed substrates; the effects of stretchable material and chip encapsulation

Stretchable printed electronics have recently opened up new opportunities and applications, including soft robotics, electronic skins, human-machine interfaces, and healthcare monitoring. Stretchable hybrid systems (SHS) leverage the benefits of low-cost fabrication of printed electronics with high-performance silicon technologies. However, direct integration of silicon-based devices on conventional stretchable substrates such as thermoplastic polyurethane (TPU) and polydimethylsiloxane (PDMS) is extremely challenging due to their restricted low-temperature processing. In this study, a recently developed thermoset, stretchable substrate (BeyolexTM) with superior thermal and mechanical properties was employed to realize SHS via direct flip chip bonding. Here, ultra-thin chips (UTC) with a fine-pitch, daisy-chain structure was flip-chip bonded by using anisotropic conductive adhesives, while the complementary circuitry was facilitated via screen-printed, stretchable silver tracks. The bonded samples successfully passed reliability assessments after being subjected to cyclic 30% stretch tests for 200 cycles. The potential benefits of chip encapsulation after integration with the stretchable substrate to withstand larger strains were demonstrated by both mechanical simulation and experimental results.

Printing of Nano‐ to Chip‐Scale Structures for Flexible Hybrid Electronics

AbstractFlexible hybrid electronics (FHE) offers potential for fast computation and communication needed in applications such as human–machine interfaces, electronic skin, etc. FHE typically comprises devices that can vary from nano‐ to chip scale, and their integration using a common process is often challenging. Herein, a printed electronics route is presented to integrate the ultrathin chips (chip‐scale) and nanowires (NWs)‐based electronic layers (nanoscale) on the same substrate. The fabrication process is categorized into three stages: i) direct transfer printing of ultrathin chips (UTCs), ii) contact printing of nanoscale structures, and iii) metal printing using the direct ink write (DIW) method to define electrodes/interconnects. The UTC printing process is carefully optimized by studying the performance of transistors present on them. Electrical data collected from 14 transistors located on 3 different chips show negligible variation in performance after they are transfer printed—thus confirming the efficacy of the printing technique. The superior grade quality of ZnO‐NWs‐based electronic layers printed on the same substrate is also demonstrated by constructing UV photodetectors using DIW printing. The photodetectors show high responsivity (≈2 × 107 A W−1) and specific detectivity (≈5 × 1015 Jones) at a low UV intensity of 0.5 µW cm−2.

Controlled Thermal Imidization of Thermoplastic Polyimide for Temporary Bonding and Debonding in Advanced Packages

Temporary bonding and debonding (TBDB) is a key technology in the semiconductor field to enable 2.5D/3D integration of devices. However, the conventional polyimides, which serve as the laser-response material in TBDB, exhibit extremely poor solubility in aprotic polar solvents due to high-temperature imidization, limiting the cleaning process for wafers after debonding. Herein, a feasible method of controlling the curing temperature to enhance the solubility of thermoplastic polyimide (TPI) has been developed. The results proved that the ultimate solubility of TPI cured at 200 °C (TPI-200 °C) could be as high as 28.4 wt %. Besides, TPI-200 °C exhibits excellent heat resistance, outstanding mechanical properties, and ultrahigh absorptivity (99.96%) at a 355 nm UV wavelength. Meanwhile, we demonstrate the feasibility of the as-prepared TPI material for application in the TBDB process, showing excellent efficiency and low cost, and the follow-up elemental analysis of the cleaned wafer surfaces proved that TPI-200 °C can be completely removed after debonding. All these results demonstrate that TPI materials that can be used for TBDB are promising for ultrathin chip packaging and wafer level packaging (WLP) in the field of advanced electronic packaging.

Sensor platforms of Alpha-fetoprotein screening test for hepatocellular carcinoma detection by Surface Plasmon Resonance technique

The objective of this paper is to present the sensor platforms for alpha-fetoprotein (AFP), detection which is a biomarker of Hepatocellular carcinoma. The experiments were designed to investigate the various platforms for AFP detection via surface Plasmon resonance (SPR) technique. In each step of the immobilization, the antiAFP-AFP interaction and enhancing signal platform was used without a fluorescent labelling on the ultra-thin film sensor chip. The result was shown that the suitable platform for AFP detection is Platform III streptavidin-biotin conjugation which gives the highest signal in both of antibody immobilization and AFP antigen detection. The detection limit of AFP detection is 10 ng/ml and the result also show that there is effect of efficiency of platform on the AFP system also the orientation between antigen and antibody.

Subsurface damage and bending strength analysis for ultra-thin and flexible silicon chips

Subsurface damage and bending strength analysis for ultra-thin and flexible silicon chips

Neuro-inspired electronic skin for robots.

Touch is a complex sensing modality owing to large number of receptors (mechano, thermal, pain) nonuniformly embedded in the soft skin all over the body. These receptors can gather and encode the large tactile data, allowing us to feel and perceive the real world. This efficient somatosensation far outperforms the touch-sensing capability of most of the state-of-the-art robots today and suggests the need for neural-like hardware for electronic skin (e-skin). This could be attained through either innovative schemes for developing distributed electronics or repurposing the neuromorphic circuits developed for other sensory modalities such as vision and audio. This Review highlights the hardware implementations of various computational building blocks for e-skin and the ways they can be integrated to potentially realize human skin-like or peripheral nervous system-like functionalities. The neural-like sensing and data processing are discussed along with various algorithms and hardware architectures. The integration of ultrathin neuromorphic chips for local computation and the printed electronics on soft substrate used for the development of e-skin over large areas are expected to advance robotic interaction as well as open new avenues for research in medical instrumentation, wearables, electronics, and neuroprosthetics.

Theoretical Modeling and Experimental Studies of Ultra-Thin Chip Transfer in Laser-Induced Forward Transfer

In order to understand and optimize the complex transfer process of ultrathin chip in laser-induced forward transfer (LIFT), a substrate–dynamic release layer (DRL)–chip structure is proposed, and a finite-element and cohesive zone model (CZM) is developed to investigate the laser ejecting needle formation and ultrathin chip peeling evolution, which is used to help analyze the impact transfer behavior of ultrathin chip in LIFT. The model considers laser absorption, conduction, volumetric expansion, and crack propagation in the substrate–DRL–chip structure. The results of the model indicate that longer laser irradiation time could produce larger maximum vapor pressure and chip transfer velocity. In addition, there are three transfer conditions in LIFT: no transfer, successful transfer, and impact fracture, which are sensitive to laser fluence. In order to achieve successful ultrathin chip transfer, an LIFT window is established and provides guidance for the appropriate laser fluence in LIFT.

Chip-scale solar thermal electrical power generation

There is an urgent need for alternative compact technologies that can derive and store energy from the sun, especially the large amount of solar heat that is not effectively used for power generation. Here, we report a combination of solution- and neat-film-based molecular solar thermal (MOST) systems, where solar energy can be stored as chemical energy and released as heat, with microfabricated thermoelectric generators to produce electricity when solar radiation is not available. The photophysical properties of two MOST couples are characterized both in liquid with a catalytical cycling setup and in a phase-interconvertible neat film. Their suitable photophysical properties let us combine them individually with a microelectromechanical ultrathin thermoelectric chip to use the stored solar energy for electrical power generation. The generator can produce, as a proof of concept, a power output of up to 0.1 nW (power output per unit volume up to 1.3 W m−3). Our results demonstrate that such a molecular thermal power generation system has a high potential to store and transfer solar power into electricity and is thus potentially independent of geographical restrictions.

Organosoluble thermoplastic polyimide with improved thermal stability and UV absorption for temporary bonding and debonding in ultra-thin chip package

Thermoplastic polyimide (TPI) has been extensively applied in electronic industry due to improved processibility, superior mechanical and dielectric properties. However, TPI is still restricted by the limited thermal stability and insufficient UV absorption for the application of temporary bonding and debonding (TBDB) in ultra-thin chip package. In this work, the rigid biphenyl group, twisted non-coplanar structure, rigid bulky side group and flexible ether bond are introduced to obtain a series of novel quaternary copolymerized TPIs with superior comprehensive performance. The results show that the as-prepared TPI possesses excellent solubility in NMP, DMF, DMAc and DMSO, and thermoplasticity (E’ drop > 103 MPa). Besides, the temperature of 5% weight loss and glass transition temperature could achieve as high as 548.1 °C and 335.4 °C, respectively. Furthermore, the tensile strength of TPI-4 is 128.7 MPa and elongation at break is about 14.2%. Moreover, the TPI-4 also exhibits superior adhesion on silicon wafer (adhesion strength >5 B by hundred grid test) and wonderful absorption at 355 nm UV laser (99.7%). At last, the application in TBDB process has also been proved with a laser energy of 400 mJ/cm2 within 60 s, showing superior efficiency and low-cost. All these results prove their application in TBDB of ultra-thin chip package for 5G era and so forth.

Ultra‐Thin Chips with Printed Interconnects on Flexible Foils

Abstract“Heterogeneous Integration” is a promising approach for high‐performance hybrid flexible electronics that combine printed electronics and silicon technology. Despite significant progresses made by integrating rigid silicon chips on flexible substrates, the integration of flexible ultra‐thin chips (UTCs) on flexible foils remains a challenge as they are too fragile for conventional bonding methods. Reliable interconnects (low‐resistivity and mechanical robustness) and bonding of UTCs are critical to the realization of hybrid flexible systems. Herein, using a non‐contact printing approach, an easy and cost‐effective method for accessing UTCs on flexible foils is demonstrated. The high‐viscosity conductive paste, extruded from a high‐resolution printer (1–10 µm line width), is used here to connect the metal oxide semiconductor field effect transistors (MOSFETs) on UTCs with the extended pads on flexible printed circuit boards (PCBs). The electrical characterization of MOSFETs, before and after printing the interconnects, reveals an acceptable level of variation in device mobility (change from 780 to 630 cm2 V−1s−1). This is due to the drop in effective drain bias voltage as a marginally small electrical resistance (≈30 Ω) is added by the printed interconnects. The bonded UTCs show robust device performance under bending conditions, indicating high reliability of both the chip thinning and bonding methods.