Ultra-thin Chips Research Articles

Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of Large-Area Electronics

This paper reports on the status of a comprehensive ten-year research and development effort toward hybrid system-in-foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity and form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on- and off-chip implementation of sensor, actuator, microwave, and energy supply components are addressed.

Screen Printing Fine Pitch Stretchable Silver Inks onto a Flexible Substrate for Wearable Applications

Abstract The lightweight and bendable features of printed flexible electronics are increasingly attractive. Currently stretchable silver inks are formulated for wide traces, typically larger than 2 mm. To attach ultra-thin silicon chips that have fine pitch onto printed organic substrate, it is necessary to print fine trace width/space that matches the pitch of the chips, which may be less than 200 microns. This paper presents the development and optimization of the screen printing process for printing stretchable silver ink onto stretchable thermoplastic polyurethane (TPU) substrate. A test vehicle was designed including 50 μm/5 mm (line width/line length) to 350 μm/35 mm lines (at 4 biases). The stretchable ink selected was DuPont PE 873 and Dupont's PE 5025 ink (non-stretchable conductive flake silver) was used as a “control” to baseline the printing process. The substrate used was Bemis TPU ST604. The experiment was done on a DEK Horizon 03i printer. A DEK squeegee 200 (Blue) and a DEK 265 flood bar (200 mm) were used. A 2-level factorial design with three replicates was selected to investigate the effect of process parameters on the quality of prints. The quality of the prints is characterized by 1) resistance of traces, 2) sheet resistance, 3) z-axis height, and 4) trace width/spacing. We observed significant noise in the z-axis printed silver ink height measured by profilometry and concluded z-axis height is not a good response variable for characterizing screen printing stretchable silver ink onto TPU substrate, mainly due to high roughness of the TPU substrate. We proposed calculated sheet resistance based on the measured resistance value, trace width, and trace length, which can replace trace height measurements on rough profile substrates. We found that squeegee pressure and emulsion thickness have statistically significant effects on calculated sheet resistance of print traces while print speed does not have statistically significant effects. In our experiment setting levels, the lower the squeegee pressure, the lower the calculated sheet resistance that is achieved. The emulsion with higher emulsion over mesh (EOM) is better than the emulsion with lower EOM since it can achieve lower sheet resistance. After optimizing the screen printing process, we were able to print 100 μm (4 mils) trace width and spacing with high consistency.

Polymer elastic bump formation through photodefinable thermal reflow process for system in foil package

In this study, hemispherical polymer elastic bumps with 200 μm diameter were formed using a highly heat-resistant photodefinable polymer to realize a system in foil package. Because polymers have a more temperature-dependent modulus than a metal, a dynamic mechanical analysis (DMA) test was performed to analyze the modulus of the polymer. The results showed that the storage modulus of the cured photodefinable polymer used for producing the polymer elastic bumps was ~3.5 GPa at room temperature, and the glass transition temperature (Tg) was 210 °C–220 °C. A single polymer elastic bump package was modeled by using the modulus values obtained from the DMA test, and the deformation under loads was analyzed using the finite element method and compared with the results for conventional copper bumps. The results showed that the bump coplanarity can be corrected easily in hemispherical polymer elastic bumps because they show large z-axis deformation under loads. The test also showed that the stress on an ultrathin chip (thickness: 20 μm) is less than half that on copper bumps. In addition, the deformation behavior depending on the metal wiring configuration on the polymer elastic bumps was analyzed under different temperature and load conditions by using a microtribometer. The analysis of the contact resistance on a single polymer elastic bump verified that the polymer can be used as a material for bumps.

Humidity and temperature sensor system demonstrator with NFC tag for HySiF applications

Abstract. Hybrid System-in-Foil (HySiF) is one of the emerging branches of flexible electronics in which ultra-thin silicon chips are integrated with flexible sensors in polymeric foils (Elsobky et al., 2018; Alavi et al., 2018). Intensive attention was given to the implementation of flexible environmental sensing platforms for logistics and food packaging (Cartasegna et al., 2011; Liu et al., 2016). The aim of this work is the implementation of a sensor system demonstrator using HySiF components, namely an ultra-thin microcontroller chip in addition to an on-chip temperature and an on-foil humidity sensors. The measurement concept for the relative humidity sensor is measuring the capacitance difference between an off-chip (on the foil substrate) humidity dependent sensor capacitor, and another humidity independent reference capacitor. The electrical readout technique is based on the charge amplifier switched capacitor circuit. It is implemented using a commercially available microcontroller (EM microelectronics EM6819) which has the advantage of being available as single chips to enable post-processing steps such as backthining and chip embedding in a thin polymer package. Sensor and reference capacitors are homogeneously integrated on-foil. 400 and 30 µm thick microcontroller dies (MCU) are used in this application. The charge amplifier result is digitized using an internal 10-bit analog-to-digital converter (ADC). The 10-bit ADC is time multiplexed between the charge amplifier structure and the internal temperature sensor. Linear interpolation is used to fit the digital output of the ADC and calibrate the output of the sensor system. Readings of the humidity level and the temperature are written to an NFC tag (from the company EM microelectronics based on chip EM NF4) using the contact interface. Readings can be accessed using a customized android application on a smartphone.

Development of ultra-thin chips for immobilization of Caenorhabditis elegans in microfluidic channels during irradiation and selection of buffer solution to prevent dehydration

BackgroundTargeted microbeam irradiation of Caenorhabditis elegans allows the effective knockdown of specific regions, thus helping to identify their roles in processes such as locomotion. We previously employed on-chip immobilization of individuals without anesthesia; however, this method was limited by the thickness of the chip, which prevented the detection of ions passing through the animal, and by dehydration of the animals after prolonged immobilization. New MethodWe developed ultra-thin, ion-penetrable, polydimethylsiloxane microfluidic chips, referred to as Worm Sheets, with and without wettability (hydrophilicity/hydrophobicity), and identified suitable buffer conditions for maintaining moisture in the microfluidic channels. ResultsUsing a collimating microbeam system, we demonstrated that carbon ions (with a range of ∼1 mm) could pass through the chip, thus allowing the ions to be detected and the applied radiation dose to therefore by measured accurately. We also examined the locomotion of C. elegans following on-chip immobilization in different buffers. Locomotion was decreased in certain buffers on unwettable chips as a result of dehydration due to evaporation, but not on wettable chips. However, locomotion was unaffected on either chip in the presence of a gelatin-based wash buffer. Comparison with Existing Method(s)We developed 300-μm-ultra-thin, wettable, ion-penetrable chips for immobilizing C. elegans and provided initial guidance regarding suitable buffer solutions to maintain moisture in microfluidic channels. ConclusionsThis improved, wettable chip, together with the identification of suitable buffer conditions, will become a powerful tool for prolonged immobilizing C. elegans, and is widely applicable not only to microbeam irradiation but also to neurobiological assays.

Adaptive Layout Technique for Microhybrid Integration of Chip-Film Patch

In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and accurate interconnecting and integrating of ultrathin chips in the polymer are feasible. The significant application of the presented accurate interconnection between the groups of functional chips is the microhybrid system-in-foil. Also, an adaptive interconnect layout at wafer-level base, allowing for a small wire pitch on and off the chip, leads to reducing silicon area and, thus, saves cost. In this paper, the process flow for embedding and integrating chips based on the adaptive layout technique is presented. The custom designed test chips are processed for the measurement and optimization of overlay accuracy of the adaptive interconnect layout regardless of the chip thickness, warpage, and topography. Besides, the electrical measurements after integrating ultrathin chips in foil confirm the interconnection between chips.

Wafer Scale Transfer of Ultrathin Silicon Chips on Flexible Substrates for High Performance Bendable Systems

AbstractThis paper presents an innovative approach for wafer scale transfer of ultrathin silicon chips on flexible substrates. The methodology is demonstrated with various devices (ultrathin chip resistive samples, metal oxide semiconductor (MOS) capacitors and n‐channel metal oxide semiconductor field effect transistors (MOSFETs)) on wafers up to 4″ diameter. This is supported by extensive electromechanical characterization and theoretical analysis, including finite element simulation, to evaluate the effect of bending and the critical breaking radius of curvature. The ultrathin chips on polyimide did not break until the radius of curvature of 1.437 mm. In the case of MOS capacitors the measured capacitance increases with increase in bending load. The changes in the transfer and output characteristics of ultrathin MOSFETs closely match with the theoretical model utilizing empirically determined parameters. Overall, the work demonstrates the efficacy of the new methodology presented here for wafer scale transfer of ultrathin chips on flexible substrates. The presented research will be useful for obtaining high performance and compact circuits needed in many futuristic flexible electronics applications such as implantable electronics and flexible displays. Further, it will open new avenues for realizing multilayered multimaterial (foil‐to‐foil) integrated bendable electronics.

Ultra‐thin smart electronic skin based on hybrid system‐in‐foil concept combining three flexible electronics technologies

Flexible electronics combined with new materials and fabrication processes offer unique characteristics such as mechanical flexibility, thin-form factor, large area scaling feasibility, and adaptability to irregular surfaces. In this work, a smart electronic skin adopting the hybrid system-in-foil concept is designed to monitor the uniaxial bending of a robotic gripper. The newly designed smart skin contains an array of printed strain gauges, organic thin-film transistor (TFT) addressing circuits and a 20 μm ultra-thin silicon readout chip, all integrated on the same polymeric foil. The silver-ink printed strain gauges achieve a relative resistance sensitivity ΔR/R of 2% and a gauge factor of 2. In addition, the organic TFT multiplexer containing a three-stage shift register and analogue switches operate at a frequency of 100 Hz and a supply voltage of 3 V. The ultra-thin silicon chip provides the functions of system control, strain gauge readout, analogue-to-digital conversion and serial communication.

Roll-to-roll processing of film substrates for hybrid integrated flexible electronics

Roll-to-roll (R2R) processing on film substrates has been demonstrated to have the potential for achieving high throughput manufacturing of organic electronic systems at low cost. However, the ever-growing mobile devices market accompanied by the developments in information and communication technologies require high performance systems at very low power operation, sometimes on larger substrates having sizes in the range of a few metres. Organic electronics often fall short of fulfilling the required computing performance and power requirements of most of the common use cases. Hybrid integration of inorganic monocrystalline silicon chips on polymer films is a means to fulfil the aforementioned requirements. In this context, it is opportune to report our recent activities on R2R processing of plastic films for hybrid integration of flexible electronics. Hybrid integration can be performed with conventional, rigid surface mount devices as well as flexible, ultra-thin bare silicon chips. The first section of the paper is dedicated to a brief overview of R2R manufacturing of electronic devices with an example of production of radio frequency identification tags as well as to a discussion emphasising the targets for hybrid integration. Then, detailed descriptions about our processes for R2R manufacturing of metal wiring lines on films and hybrid integration are included. Three-dimensional integration of films and a temperature sensor label manufactured using hybrid integration process are also elaborated on. Furthermore, key results from fatigue reliability assessment of R2R metallised wiring lines are reported. Finally, some of the challenges in transferring the R2R processes for hybrid integration on film substrates from research labs to industrial manufacturing are highlighted.

Theoretical and Experimental Studies of Competing Fracture for Flexible Chip-Adhesive-Substrate Composite Structure

Competing fracture of chip peeling and chip cracking dominates the fast, nondestructive, and reliable peeling of ultrathin silicon-based chip from polymeric substrate. Here, a competing fracture model of chip-adhesive-substrate composite structure is developed to achieve the successful chip peeling in needle ejecting process. Influences of the thickness and length of chip and layout of ejector needle on the peeling-off behavior are investigated. The theoretical prediction is found agreed well with both numerical simulation and experimental test. The process window is preliminarily determined by combining the designed experimental platform. The traditional needle ejecting process is found helpless to achieve the purpose of nondestructive peeling off for an ultrathin chip. A modified multineedle ejecting process with independently controlled ejector needles is finally proposed to improve the chip peelability.

Heat-Depolymerizable Polypropylene Carbonate as a Temporary Bonding Adhesive for Fabrication of Flexible Silicon Sensor Chips

This paper presents a method for fabrication of flexible silicon sensor chips using temporary bonding, backside thinning, debonding, and flexible packaging. Flexibility of silicon chips requires ultrathin thickness, which imposes a challenge to debonding of thinned silicon chips from carrier wafers because of the fragility of silicon. To address this problem, temporary bonding using polypropylene carbonate (PPC), a heat-depolymerizable polymer material, as bonding adhesive is developed. PPC allows damage-free detachment of ultrathin silicon chips from carrier wafers by heating after backside thinning. The method is demonstrated and applied to the fabrication of silicon stress sensor chips with thickness down to $30~\mu \text{m}$ . The measurement results show that the ultrathin silicon chips have good flexibility and function well. The processes are optimized, and the detailed parameters are reported. The preliminary results demonstrate the feasibility of the method, and show its potential application in the fabrication of flexible ultrathin silicon sensors.

Measurement-Based Compact Thermal Model Extraction Methodology for Packaged ICs

In this paper, a rigorous methodology for extracting the thermal compact model parameters of packaged chips is presented. The methodology is based on using a custom-designed test chip with multiple heating and temperature sensing elements in order to predict the temperature distribution in packaged chips after packaging. The technique involves measurement of various chips with different thicknesses, different packages, and for different power dissipation scenarios through which the thermal model parameters can be extracted. The results show that ultrathin chips with a total thickness below $20~\mu \text{m}$ experience a dramatically increased temperature for localized heat dissipation. In addition to this, the measurements conducted in time domain and frequency domain show that at high enough frequencies of heat pulsing, the temperature variations become independent of the thermal boundary conditions of the chip. The measurement results are compared to the finite-element method simulation data. The simulations together with the measurement methodology serve as a technique to extract the thermal compact model parameters of packaged chips after being fabricated and packaged in an accurate and efficient way.

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

Abstract. Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

On-chip cell analysis platform: Implementation of contact fluorescence microscopy in microfluidic chips

Although fluorescence microscopy is the gold standard tool for biomedical research and clinical applications, their use beyond well-established laboratory infrastructures remains limited. The present study investigated a novel on-chip cell analysis platform based on contact fluorescence microscopy and microfluidics. Combined use of a contact fluorescence imager based on complementary metal-oxide semiconductor technology and an ultra-thin glass bottom microfluidic chip enabled both to observe living cells with minimal image distortion and to ease controlling and handling of biological samples (e.g. cells and biological molecules) in the imaged area. A proof-of-concept experiment of on-chip detection of cellular response to endothelial growth factor demonstrated promising use for the recently developed on-chip cell analysis platform. Contact fluorescence microscopy has numerous desirable features including compatibility with plastic microfluidic chips and compatibility with the electrical control system, and thus will fulfill the requirements of a fully automated cell analysis system.

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

Modeling of CMOS Devices and Circuits on Flexible Ultrathin Chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18- $\mu \text{m}$ technology were fabricated in two separated chips. The two fabricated chips were thinned down to $20~\mu \text{m}$ using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch).

Fast Nonlinear Dynamic Compact Thermal Modeling With Multiple Heat Sources in Ultra-Thin Chip Stacking Technology

This paper presents a model-order reduction technique to extract nonlinear dynamic compact thermal models (DCTMs) with multiple (>1) heat sources. The approach leads to nonlinear DCTMs of small state-space dimensions that allow accurately reconstructing the whole temperature and heat flux fields induced by arbitrary power waveforms in complex structures composed of many materials with thermal conductivities showing different values and temperature dependences. The DCTM extraction requires a small fraction of the CPU time needed for the simulation of a power step response using the finite element method (FEM), while ensuring a very high level of precision. Therefore, the adoption of the proposed strategy is a viable alternative to FEM for performing efficient and accurate nonlinear transient analyses: The advantage of using a DCTM is magnified if many power input waveforms have to be considered for the same structure since any further simulation of the extracted DCTM is nearly instantaneous. As a case study, the proposed technique is used to investigate the impact of two cooling solutions on the thermal behavior of a three-die module in ultra-thin chip stacking technology.

Device Modelling for Bendable Piezoelectric FET-Based Touch Sensing System

Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable piezoelectric oxide semiconductor field effect transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog- A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin).

Analysis of Interfacial Peeling of an Ultrathin Silicon Wafer Chip in a Pick-Up Process Using an Air Blowing Method

The ultrathin integrated circuit (IC) chip ejecting and pick-up process plays an important role in advanced packages since the success ratio and productivity are determined by the delamination of chips from the adhesive tape substrate. As thinning of the IC chip occurs, chip cracking between the adhesive tape and ultrathin IC chip increases due to the low strength of the ultrathin IC chip in the die pick-up process. In this paper, the interfacial adhesion strength and energy release rate between an ultrathin IC chip and base tape were measured by a 90° peel test as a function of the peeling velocity. Also, an index was defined to characterize the competing fracture behavior between the delamination of the chip from the adhesive tape and chip cracking. Finite-element analysis of the die pick-up process with a virtual crack-closure technique was performed to predict stable peeling off of the chip with respect to the velocity of the chip holder as well as the pressure of the blown air considering the interfacial energy release rate and chip strength. The results show that the velocity of the chip holder and the pressure of the blown air should be lower than 50 mm/min and 90 kPa, respectively.

Analytical investigation on thermal-induced warpage behavior of ultrathin chip-on-flex (UTCOF) assembly

The serious warpage issues of ultrathin chip-on-flex (UTCOF) assembly induced by mismatched thermal stresses have greatly affected the mechanical stability and reliability of emerging ultrathin chip packaging technology. Currently, a theoretical prediction as a convenient and straightforward approach is still lacked for describing effectively the thermal-mechanical behavior of UTCOF during the adhesive curing and cooling process. In consideration of the adhesive thickness approximating to ultrathin chip and flexible substrate thickness, we develop a layerwise-model of ultrathin chip-adhesive-flex structure under plain strain condition, where the behavior of thick adhesive bonding can be described precisely through increasing the subdivided mathematical plies. Further, the analytical results show that the concave and convex forms of ultrathin chip warpage yield at the end of the curing and cooling process respectively. Meanwhile, the effects of its structure dimensions and material properties are also revealed for discussing a way to relieve the extent of ultrathin chip warpage. Additionally, in order to verify the validity of the theoretical prediction, we also introduce the corresponding numerical technique and experimental method. These results suggest that a kind of rigid and ultrathin flexible substrate such as metal foil should be adopted for small warpage of ultrathin assembly.