Ultra-low Supply Voltage Research Articles

Reliable single-ended ultra-low power GNRFETs-based 9T SRAM cell with improved read and write operations

This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area. Therefore, the power consumption and area of the proposed cell is enhanced by 48.9 % and 3.8 %, respectively, as compared to the 2-bitline (2-BL) 9T SRAM cell. A separate read and write port provides significant improvement in the read and write performance simultaneously. The performance of the proposed cell and other existing cells are evaluated using HSPICE-simulations. The multi-threshold technology is used to improve the performance of cells in terms of delay and power consumption. The proposed cell shows significant improvement in read stability and write-ability due to proper device sizing ratio. In nanometer regime, the cell is capable to operate at ultra low supply voltage of 300 mV due to outstanding electrical property of the GNRFETs devices.

Printed organic transistors and complementary ring oscillators operatable at 200 mV

Applications of organic thin-film transistors (OTFTs) include wearable health monitors and next-generation Internet-of-Things systems driven by a small energy-harvesting power supply. Such applications require low voltage and low power consumption organic ICs. In this paper, we demonstrate complementary ICs based on printed p-type and n-type OTFTs operatable at an ultralow supply voltage of 200 mV. For that purpose, threshold voltages were finely tuned by dual-gate structure and self-assembled monolayer. Complementary inverter-based ring oscillators operated at small supply voltages down to 200 mV and exhibited a power consumption as small as 6 pW per stage.

Temperature Sensor with Buffer-Chain based Time-to-Digital Converter for Ultra-Low Voltage Operation

This paper proposes a Time-to-Digital Converter (TDC) based temperature sensor that aims to operate with an ultra-low voltage electromotive force for IoT applications with energy harvesting. Sub-threshold circuit design was exploited for the operation at ultra-low supply voltage. The proposed circuit uses the characteristics of leakage current for temperature measurement. The virtual ground node in the proposed sensor is charged up by leakage current and the charging time changes with the temperature. To measure the temperature-dependent charging time, we used a buffer-chain based TDC to achieve ultra-low voltage operation. Simulation results demonstrated that the minimum supply voltage for the proposed circuit is 0.15V. The power consumption is 407nW and sensing time is 180ns at 25℃. The measurable temperature range is from -40℃ to 85℃. The proposed circuit was designed with Renesas SOTB 65nm process. Simulation evaluation was conducted using HSPICE.

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3

In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as the first gain stage and an active primary–secondary amplifier as the second gain stage, achieving an imperceptible flicker-noise corner frequency. With the SC gain stage, the interstage common-mode voltage can be set to 0 V, which reduces the minimum supply voltage to 0.5 V. As another benefit, dc offset compensation (DCOC) is performed inherently in the interstage sampling and coupling process. Fabricated in 28-nm RF CMOS process, the front-end prototype, including an on-chip matching inductor, occupies a die area of 0.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Operating in the Industrial Scientific Medical (ISM) frequency band of 2.4 GHz with 1-MHz IF bandwidth, the front end provides a 36–40-dB conversion gain, an 11.5-dBm OIP3, and a flicker-noise corner frequency less than 10 kHz with the supply voltage ranging from 0.5 to 0.6 V. The RF impedance matching network provides passive voltage gain before the low-noise trans-conductance amplifier (LNTA), achieving a 4.5-dB noise figure (NF) with 0.8-mA biasing current in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_m$</tex-math> </inline-formula> stage. With the ultra-low supply voltage and the passive IF gain stage, the power consumption of the proposed front end is only 610 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> W under a 0.53-V supply voltage.

A Picowatt CMOS Voltage Reference Operating at 0.5-V Power Supply With Process and Temperature Compensation for Low-Power IoT Systems

This brief presents a picowatt PVT-insensitive CMOS voltage reference with ultra-low supply voltage. The core circuit of the proposed reference consists of three subthreshold-biased PMOS transistors, and process and temperature compensation are achieved by employing the width-induced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ th}}$ </tex-math></inline-formula> modulation and self-body-biasing techniques. The reference was implemented in a standard 180-nm CMOS process. With a power supply of 0.5 V at 25 °C, the measurement results of 16 chips show a mean reference voltage of 288 mV with a standard deviation of 1.65 mV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(\sigma /\mu \,\,=$ </tex-math></inline-formula> 0.57%). The line sensitivity is 0.23%/V with a minimum supply voltage of 0.5 V. The average temperature coefficient is 90 ppm/°C after batch trimming over a temperature range of −10°C to 100°C. The power consumption at room temperature is 500 pW, and the active area is 0.0029 mm2.

Speed and Scalability of Ambipolar Deep-Subthreshold TFTs for Ultralow-Power Printed Electronics

This work evaluates the speed and scalability potential of ambipolar deep-subthreshold printed-carbon-nanotube thin-film transistors (CNT-TFTs) for the design of ultra-low-power CMOS-like circuits. Transistor and circuit simulations are developed based on experimental device measurements. Our simulations allow the assessment of this emerging printed electronics technology in terms of speed, energy/power consumption and scalability to digital circuits of progressively higher transistor count including elementary logic gates, ring-oscillators and other representative digital circuits. It is shown that digital circuits based on this technology are compatible with propagation delays ≤ 1 ms per NOT logic gate, while operating at ultra-low supply voltages (0.2 V) and with ultra-low static power dissipation (1 pW). Finally, this study develops Monte Carlo simulations to assess the impact of device parameter variations on the viability of large-scale circuit integration based on ambipolar deep-subthreshold printed-CNT-TFTs.

A 0.3-V, −75.8-dBm Temperature-Robust Differential Wake-Up Receiver for WSNs

This article presents a 0.3-V, −75.8-dBm differential wake-up receiver (WuRX) with temperature robustness for wireless sensor network (WSN) applications. In this work, an adaptive gate-biased pseudo-differential envelope detector (ED) with temperature compensation is proposed to achieve high conversion gain, wide range of tunability, and temperature robustness at the cost of low power consumption. To address the problem that the high supply voltage of the baseband amplifier (BB-AMP) limits the further reduction of the overall system supply voltage, a bulk-driven differential BB-AMP is also proposed, the characteristics of its ultralow supply voltage make the system supply voltage as low as 0.3 V. And the dual path offset calibration loop is proposed to eliminate all mismatches and offsets in the differential signal path, further ensuring the system robustness. This WuRX is implemented in a 65-nm LP CMOS process, operates at 434 MHz, consumes 6.96 nW from 0.3-V supply voltage, and achieves a sensitivity of −75.8 dBm at 250 bps. When the temperature changes from −10 °C to 50 °C, the sensitivity varies from −77.5 to −73.6 dBm.

A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range

In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$121.8\times $ </tex-math></inline-formula> under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests.

A 0.25-V 90 dB PVT-stabilized four-stage OTA with linear Q-factor modulation and fast slew-rate enhancement for ultra-low supply ADCs

A high gain and stability, four-stage OTA with a linear transistor Q-factor modulation compensation (TQM) and a fast, power-constrained slew-rate enhancement (PC-SRE) is proposed for ADCs working under ultra-low supply voltage. A rail-to-rail input & output bulk-driven fully differential four-stage operational amplifier with proposed structure is also presented under 0.25 V supply voltage. By using proposed structure, the response speed and stability of designed four-stage amplifier have been greatly improved. The effectiveness of the circuit has been verified in standard 65 nm CMOS process, the proposed three-stage amplifier has 90.9 dB DC-gain, 31.2 kHz unity-gain frequency, and 78.2° phase margin while consuming 32.8nW power, and occupying chip area of 0.00082 mm2 from a 0.25 V supply while driving a 100pF load.

Ultralow Power K-Band Frequency Doubler With Differential Output

This article presents an ultralow power K-band frequency doubler operating under 0.4-V supply voltage. With 0-dBm input signal, the frequency doubler consumes 2.4 mW and achieves −8.4-dB conversion gain (CG). The measured saturated output power is −6 dBm at 23.6 GHz, and the 3-dB bandwidth is from 20.4 to 25.4 GHz. It exhibits up to 39-dB fundamental rejection (FR). The proposed differential frequency doubler operates at an ultralow supply voltage with ultralow power consumption in active frequency doublers.

Analysis and Design of the Three-Inverter Schmitt Trigger for Supply Voltages Down to 50 mV

This brief analyzes the operation of the three-inverter Schmitt trigger (TI-ST) at ultra-low supply voltages. Included in the analysis is a model to predict the supply voltage at which the TI-ST changes from the amplifier mode to the hysteresis mode. We show theoretically that the TI-ST can exhibit hysteresis for a supply voltage as low as the fundamental limit of unity gain of the CMOS inverter. We also demonstrate experimentally that, with a suitable design, hysteresis starts to occur from a supply voltage as low as 48.5 mV. A relaxation oscillator built with a TI-ST and standard inverters is experimentally demonstrated to start to oscillate from supply voltages as low as 62 mV.

Flexible low-voltage organic thin-film transistors and PMOS inverters: the effect of channel width on noise margin

Low-operating-voltage (<2 V) organic thin-film transistors (OTFTs) and P-channel metal-oxide-semiconductor (PMOS) inverter circuits are fabricated on a 125 µm-thick flexible polyethylene naphthalate substrate using a blend of 2,7-dihexyl-dithieno[2,3-d;2′,3′-d′]benzo[1,2-b;4,5-b′]dithiophene and polystyrene as an active p-type organic semiconducting material. All three electrodes (gate, source, and drain) are inkjet-printed, while the active semiconducting material is deposited by a dispenser system to achieve a saturation mobility of 0.32 cm2 V−1 s−1 at V GS = −2 V. Two different PMOS inverters are fabricated, for which the signal gain peak values are resolved for an ultra-low supply voltage, V DD = −0.5 V. We achieve a signal gain of 2.73 at V DD = −0.5 V. The effect of channel width is demonstrated for both OTFTs and PMOS devices. The ‘on’ current increases with channel width, and the switching point of the PMOS inverters shifts toward the middle of the voltage transfer characteristics, and hence improves the noise margin.

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications

A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers. By using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved. By using this compensation method, a rail-to-rail input & output bulk-driven fully differential operational amplifier is also presented in the paper. The effectiveness of the circuit has been verified in a 65 nm CMOS process, the proposed three-stage amplifier has over 70.69 dB gain, 19.95 kHz gain-bandwidth product, and 69.7° phase margin while consuming only 8.72 nW power, and occupying die area of 0.00082 mm2 from a 0.3 V supply while driving a 100pF load.

Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop

This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in the range of 0.3–0.5 V. In particular, a dc voltage gain of 25.16 dB, a gain-bandwidth product of 131.9 kHz with a capacitive load of 10 pF, and a static current consumption of only 557 nA are estimated at VDD = 0.5 V. Moreover, the circuit behavior with respect to process and temperature variations was verified. Finally, the proposed amplifier is employed in a switched-capacitor integrator and in a sample-and-hold circuit to prove its functionality in case-study applications.

Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

In this article, we propose a novel nanotube (NT) tunneling field-effect transistor with a core source (CSNT-TFET) which uses line tunneling. We systematically investigate the CSNT-TFET with the help of calibrated 3-D simulations and demonstrate that it outperforms the conventional NT-TFET in terms of both static and dynamic performance. We show that the CSNT-TFET exhibits a reduced average subthreshold swing (SS) of 33 mV/decade with Ge-source for more than eight orders of magnitude of drain current at an ultralow supply voltage ( ${V}_{\text {DS}}= {0.3}$ V). In addition, the ON-state current of the CSNT-TFET is enhanced by ~13 times with Si-source and by ~6 times with Ge-source even at ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V when compared with the NT-TFET. Without the use of any exotic material for the source and channel regions, the CSNT-TFET offers an impact ionization MOS-like steep SS (a minimum SSpoint of ~1 mV/decade) and a high ON-state current of ~10−6 A for ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V. Furthermore, the impact of the gate sidewall spacer and source diameter on the performance of the CSNT-TFET is also investigated.

A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique

This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes $3.09~{\boldsymbol{\mu }}\text{W}$ . The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS

A 9-GHz sub-integer frequency synthesizer incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5 V, phase-switching-based programmable division for sub-integer frequency synthesis, and automatic calibration to ensure injection lock. The synthesizer consumes 3.5 mW of power at 9.12 GHz and 0.05 mm2 of area, while showing an output phase noise of −100 dBc/Hz at 1 MHz offset and RMS jitter of 325 fs; it achieves a net FOMA of −186.5 in a 45-nm SOI CMOS process.

A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems

In this paper, we propose an ultra-low power compact 3-transistor voltage reference capable of operating at ultra-low supply voltages. The proposed circuit is based on the self-cascode MOSFET (SCM), which provides a reference voltage proportional to the threshold voltage ( $V_{T}$ ) difference of the two NMOS transistors that compose it. Reverse short-channel and narrow-width effects are explored to obtain such $V_{T}$ difference while using the same type of transistor. Ultra-low power operation and low line sensitivity is achieved by biasing the SCM with a zero- $V_{T}$ (native) transistor, also leading to an area efficient design. To show its versatility, three versions of the proposed circuit were fabricated in a standard 0.13- $\mu \text{m}$ CMOS process. Measurement performed over five samples showed an average temperature coefficient of 150–1500 ppm/°C. Minimum supply voltages of 0.12–0.4 V was observed while providing reference voltages around tens of mV. The proposed circuits consume 0.33–50 pW at room temperature and minimum supply voltage. The occupied area for any version is less than 0.0012 mm2.

Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method

Reliability is one of the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques have been applied to logic circuits to resist random noise when operating under ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks can be easily mapped onto simple logic circuits, it becomes difficult when the circuits are large and complex. In this paper, we present a general coding-based partial MRF (CPMRF) method for multi-logic operations in one basic unit, which is referred to as a CPMRF pair. A CPMRF pair saves circuit area by sharing a common MRF network. It also inherits noise immunity from the MRF theory while obtaining noise immunity from the coding structure as a combination of robust “1s” and “0s.” The resulting architectures become more cost effective than conventional ones. To validate the performance of our proof-of-concept design, we fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM 130-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20% improvement while occupying 37.7% less area and reducing power consumption by 93% compared with the master-and-slave MRF CLA design.