Ultra-low Power Systems Research Articles

Модификация наноструктурированного диоксида титана методом гидротермальной обработки для улучшения электрических параметров бета-вольтаических элементов

New technologies of microelectronics are emerging to reduce the size of devices and combine them into more compact ultra-low power systems. Betavoltaic power sources (BVPSs) can serve as power generators of such order. BVPSs consist of a combination of betavoltaic cells (BVCs) based on long-lived radioisotopes of beta radiation and semiconductor converters (SCs). One of the key tasks for increasing the power of BVC is the selection of SCs that can efficiently convert the energy of beta particles into electricity. Currently, semiconductor structures with a developed surface and a high band gap are considered to be perspective SCs. In present work, arrays of titanium dioxide nanopores (TiO2 NPs) synthesized by common electrochemical anodization was chosen as a SCs. These SCs were part of BVCs based on nickel-63 with an activity of ~ 10 Ci/g. TiO2 NPs with an amorphous structure in the composition of BVC demonstrated low electrical parameters. To increase them, we modified TiO2 NPs by the hydrothermal method in a solution of Sr(OH)2 with a concentration of 0.05 mol/l at various times. These experiments were carried out in order to convert TiO2 (anatase) into structure-like SrTiO3. We found that the electrical parameters of the SCs increased with the duration of the modification time. The best result was obtained in case of 3 h modification — the BVC generated a short circuit current 2,9 nA, open circuit voltage 0,8 V and had a maximum power 0,8 nW at 0,45 – 0,5 V. The obtained electrical parameters in combination with the miniature dimensions of the BVCs open up the potential possibility of creating a BVPS with an increased power density.

Ultra-low power logic in memory with commercial grade memristors and FPGA-based smart-IMPLY architecture

Reducing power consumption in nowadays computer technologies represents an increasingly difficult challenge. Conventional computing architectures suffer from the so-called von Neumann bottleneck (VNB), which consists in the continuous need to exchange data and instructions between the memory and the processing unit, leading to significant and apparently unavoidable power consumption. Even the hardware typically employed to run Artificial Intelligence (AI) algorithms, such as Deep Neural Networks (DNN), suffers from this limitation. A change of paradigm is so needed to comply with the ever-increasing demand for ultra-low power, autonomous, and intelligent systems. From this perspective, emerging memristive non-volatile memories are considered a good candidate to lead this technological transition toward the next-generation hardware platforms, enabling the possibility to store and process information in the same place, therefore bypassing the VNB. To evaluate the state of current public-available devices, in this work commercial-grade packaged Self Directed Channel memristors are thoroughly studied to evaluate their performance in the framework of in-memory computing. Specifically, the operating conditions allowing both analog update of the synaptic weight and stable binary switching are identified, along with the associated issues. To this purpose, a dedicated yet prototypical system based on an FPGA control platform is designed and realized. Then, it is exploited to fully characterize the performance in terms of power consumption of an innovative Smart IMPLY (SIMPLY) Logic-in-Memory (LiM) computing framework that allows reliable in-memory computation of classical Boolean operations. The projection of these results to the nanoseconds regime leads to an estimation of the real potential of this computing paradigm. Although not investigated in this work, the presented platform can also be exploited to test memristor-based SNN and Binarized DNNs (i.e., BNN), that can be combined with LiM to provide the heterogeneous flexible architecture envisioned as the long-term goal for ubiquitous and pervasive AI.

Mobile-BAT-A Novel Ultra-Low Power Wildlife Tracking System.

We introduce a novel ultra-low power system for tracking animal movements over long periods with an unprecedented high-temporal-resolution. The localization principle is based on the detection of cellular base stations using a miniaturized software-defined radio, weighing 2.0 g, including the battery, and having a size equivalent to two stacked 1-euro cent coins. Therefore, the system is small and lightweight enough to be deployed on small, wide-ranging, or migrating animals, such as European bats, for movement analysis with an unprecedented spatiotemporal resolution. The position estimation relies on a post-processing probabilistic RF pattern-matching method based on the acquired base stations and power levels. In several field tests, the system has been successfully verified, and a run-time of close to one year has been demonstrated.

Ultralow-Power Sensing Framework for Internet of Things: A Smart Gas Meter as a Case

Gas serves as one of the most indispensable energy sources for industrial production and household life. In order to improve the gas utilization efficiency, smart gas meters for the Internet of Things (IoT) has been designed to achieve two-way communication and remote control functions. However, the existing smart gas meter does not consider further reduction of power consumption. Thus, we designed an ultralow-power sensing framework for IoT and applied it to the smart gas meter. Based on a thorough analysis of the metering system, we propose an ultralow power system framework and a low-power peripheral management solution to reach ultralow power consumption. Also, we propose a cooperative sensing scheme to achieve stability and accuracy of gas volume detection. Finally, we implement a real smart gas manage system to evaluate our low-power smart gas meter solution. Verified by a comparative test, the proposed gas meter successfully reduces the power consumption by at least 37% compared to the baseline. The experimental results verify the innovative design and confirm that the proposed gas meter features ultralow power consumption, high precision, and high reliability.

An Ultra-Low Power, Small Size and High Precision Indoor Localization System Based on MEMS Ultrasonic Transducer Chips.

The development of Internet of Things (IoT) requires demanding accurate and low-power indoor localization. In this article, a high-precision 3-D ultrasonic indoor localization system with ultralow power is proposed. A new piezoelectric micromachined ultrasonic transducer (PMUT) chip with a slotted membrane is designed and fabricated as a receiver, breaking the dilemma of low resonant frequency and wide field of view required for indoor localization. The system works based on the time difference of arrival (TDoA), and an improved quantum genetic algorithm (QGA) is used to estimate the location. The results show that the system achieves centimeter-level positioning precision, which is among the best solutions nowadays. Due to the high performance and small size endowed by the PMUT, the receiver footprint reaches as small as 0.25 cm2 and power consumption could reach as low as 0.1 mW, which are far better than that of current indoor localization systems.

Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.

TEI-DTA: Optimizing a Vehicular Sensor Network Operating with Ultra-Low Power System-on-Chips

In the era of the Internet of Things (IoT), the interest and demand for embedded systems have been explosively increasing. In particular, vehicular sensor networks are one of the fields where IoT-oriented embedded devices (also known as IoT devices) are being actively used. These IoT devices are widely deployed in and out of the vehicle to check vehicle conditions, prevent accidents, and support autonomous driving, forming a vehicular sensor network. In particular, such sensor networks mainly consist of third-party devices that operate independently of the vehicle and run on their own batteries. After all, like all battery-powered embedded devices, the IoT devices for the vehicular sensor network also suffer from limited power sources, and thus research on how to design/operate them energy-efficiently is drawing attention from both academia and industry. This paper notes that the vehicular sensor network may be the best application for ultra-low power system on-chips (ULP SoCs). The ULP SoCs are mainly designed based on ultra-low voltage operating (ULV) circuits, and this paper aims to realize the energy-optimized driving of the network by applying state of the art (SoA) low-power techniques exploiting the unique characteristics of ULV circuits to the IoT devices in the vehicular sensor network. To this end, this paper proposes an optimal task assignment algorithm that can achieve the best energy-efficient drive of the target network by fully utilizing the SoA low power techniques for ULV circuits. Along with a detailed description of the proposed algorithm, this paper demonstrates the effectiveness of the proposed method by providing an in-depth evaluation process and experimental results for the proposed algorithm.

Modeling Periodic Energy-Harvesting Computing Systems

The Internet of Things (IoT) requires Ultra-Low Power (ULP) systems that communicate wirelessly and solely rely on harvested energy to scalably interact with the environment. This is challenging for IoT developers because (i) energy and performance are fundamentally intertwined — since capturing sensor samples and communicating more frequently increases energy consumption — and (ii) the performance versus energy trade-off typically needs to evaluated before ULP-platform selection — as the developer needs to be sure that a sufficiently performant system can be built before incurring the (substantial) effort of implementing the application on the ULP-platform. In this paper, we present the Periodic Energy-Harvesting Systems (PES) model which enables such trade-offs by faithfully modeling the energy impact of changing sampling and communication rates. Across our IoT applications, PES has an average energy prediction error of only 0.5%. In contrast, the average error of the state-of-the-art EH-model is 77.0%.

Low Power Circuit and System Design Hierarchy and Thermal Reliability of Tunnel Field Effect Transistor

Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been addressed here. The temperature reliability investigation is based on double gate Tunnel FET, containing Si1-xGe x /Si, source/channel and HfO2 high-k gate dielectric material. During investigation, it has been found that at high temperature application range ~ 300 K - to - 600 K,the Tunnel FET device design parameters exhibit weak temperature dependency with switching current (ION), while the off-state current (IOFF) is slightly varying ~10−17A/μm-to-10−10A/μm. In addition, the impact of temperature on various device design element such as VTH(i.e.,switching voltage),on-current (ION), off-current (IOFF), switching ratio (ION/IOFF) and average subthreshold slope (i.e., SSavg), ambipolar current (IAMB) have been done in this research work.The essential circuit design components for digital and analog/RF applications, such as current amplification factor(gm) and its derivative (gm’),the C-V components of device design, Cgg, Cgd and Cgs, cut - off frequency (ƒT) and gain band width (GBW) product have deeply investigated. In conclusion, the obtained results show that the designed double gate Tunnel FET device configuration and its circuit design components are suitable for ultra-low power circuit,system applications and reliable for hazardous temperature environment.

Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application

In this paper Junctionless Double Gate MOSFET based Efficient Charge Recovery Logic (JL-ECRL) circuits have been driven in sub-threshold regime for the first time in literature to implement the ultra low power systems where the performance is not pivotal issue. Analytical modeling of the power dissipation, delay and the power delay product (PDP) of the sub-threshold JL-Inverter structure have been detailed out. Impact of supply voltage, temperature and the variation of the process parameters like oxide thickness, silicon thickness, doping concentrations have been discussed in depth. Extensive simulations have been done using SILVACO ATLAS to validate analytical data of the power, delay and PDP of the proposed model for different channel length. Based on the analytical and simulated data, optimum conditions have been chosen for the proposed model. It has been observed that the proposed model can perform efficaciously in sub threshold regime without sacrificing noise immunity.

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

This paper presents Mr.Wolf, a parallel ultra-low power (PULP) system on chip (SoC) featuring a hierarchical architecture with a small (12 kgates) microcontroller (MCU) class RISC-V core augmented with an autonomous IO subsystem for efficient data transfer from a wide set of peripherals. The small core can offload compute-intensive kernels to an eight-core floating-point capable of processing engine available on demand. The proposed SoC, implemented in a 40-nm LP CMOS technology, features a 108-μW fully retentive memory (512 kB). The IO subsystem is capable of transferring up to 1.6 Gbit/s from external devices to the memory in less than 2.5 mW. The eight-core compute cluster achieves a peak performance of 850 million of 32-bit integer multiply and accumulate per second (MMAC/s) and 500 million of 32-bit floating-point multiply and accumulate per second (MFMAC/s) -1 GFlop/s-with an energy efficiency up to 15 MMAC/s/mW and 9 MFMAC/s/mW. These building blocks are supported by aggressive on-chip power conversion and management, enabling energy-proportional heterogeneous computing for always-on IoT end nodes improving performance by several orders of magnitude with respect to traditional single-core MCUs within a power envelope of 153 mW. We demonstrated the capabilities of the proposed SoC on a wide set of near-sensor processing kernels showing that Mr.Wolf can deliver performance up to 16.4 GOp/s with energy efficiency up to 274 MOp/s/mW on real-life applications, paving the way for always-on data analytics on high-bandwidth sensors at the edge of the Internet of Things.

A 0.5-V-supply, 37.8-nW, 17.6-ppm/°C switched-capacitor bandgap reference with second-order curvature compensation

This paper presents a switched-capacitor (SC) bandgap reference (BGR) with second-order curvature compensation for ultra-low power systems. The gate-source voltage of a sub-threshold MOSFET is proposed to implement the second-order curvature compensation voltage in this work. And then, a SC network is used, not only to add the second-order voltage and the first-order one together, but also to fulfill the summing weight effectively and precisely. In this way, the silicon area and power consumption can be reduced simultaneously. Furthermore, the design methodology of summing weight is investigated, and thus the temperature coefficient (TC) can be significantly reduced. The proposed SC-BGR was implemented and simulated in a CMOS 0.18 μm process, the average output voltage is 426.1 mV, achieving a TC of 17.6 ppm/°C from −20 to 100 °C under a 0.5 V minimum supply voltage. With the help of the SC architecture, a small chip area of 0.0975 mm2 is achieved with only 37.8-nW power consumption.

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

Body bias control is one of the most efficient means to reduce leakage power, adjust process variation, and apply performance boost. However, such control incurs a certain power overhead that has to be reduced, especially in ultra low-power systems. In order to exploit the advantages of body bias control while guaranteeing power efficiency, an on-chip control scheme is required. Conventionally, on-chip body bias control relies on the use of digital–analog converters. However, such analog circuits require a high power supply voltage and an additional power source, resulting in a considerable power overhead and an increased system cost. In this paper, an on-chip “Digitally assisted Automatic Body-bias Tuning” (DABT) scheme for ultra low-power systems is proposed and evaluated. The proposed scheme controls the body bias voltage so as to meet the timing constraints of a given target system. Since DABT is based on “Digitally assisted” circuitries, it can decrease the power supply voltage to near-threshold region and, therefore, a significant amount of power overhead can be reduced. The proposed system is fabricated with the 65-nm silicon on thin box (SOTB) process, a fully depleted silicon on insulator technology. We demonstrate that the chip can achieve the expected functionality, even with 0.35 V of power supply voltage, and with only a few micro watts of power overhead. Moreover, the efficiency of the proposed system is evaluated with a MIPS processor, adopted as a case study. According to the obtained evaluation results, the proposed system can enable 80% of leakage reduction while maintaining the frequency required to meet the timing constraints of the adopted target MIPS processor.

Modeling of polyurethane/lead zirconate titanate composites for vibration energy harvesting

Collecting the vibration energy existing in the surrounding environment and its transformation to a useful electrical energy in order to supply ultra-low power systems remains an emerging and promising technology. During the last decades, most of research efforts dealt with energy-harvesting technology using piezoelectric ceramics. However, those materials are stiff and limited in mechanical strain abilities. In addition, they lose their stiffness and piezoelectricity at high levels of mechanical strain. Thus, they are unsuitable for many applications in which low frequency and high strain level are required. However, electrostrictive polymers are lightweight, very flexible, have low manufacturing costs and are easy to mould into any desired shapes. These special properties led to them being considered as potential actuators. However, it is not well known that these materials also can be used for mechanical-to-electrical energy harvesting. In this research paper, electromechanical characterization of polymer/lead zirconate titanate composites was extended. The first part develops the analytical model predicting the energy harvested by polyurethane/PZT composites from electrical and mechanical properties of their constituent materials. Indeed, this model was based on the approach of representing the experimental setup with an equivalent electrical scheme. The second part focuses on the assessment of model performance by comparison between predicted and observed values. As a result, good agreements were observed between the two sets of data; in addition, the model could be used to optimize the choice of constituent materials. The last part concerns the contribution of both the electrostrictive effect and piezoelectric effect in electrical powers harvested by PU/PZT composites.

Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications

ABSTRACTClock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. Sub-threshold operation of devices is an excellent option to have an ultra-low power system. However, degraded performance and exacerbated variability are the major concerns of the sub-threshold circuits. Furthermore, as contradictory to the conventional super threshold circuits, the device resistance for the sub-threshold circuits is quite high compared to the interconnect resistance. This paper therefore, explores the design constraints for sub-threshold clock system. It further explores the suitability of buffered and un-buffered clock system in deep sub-threshold regime. The impact of supply voltage scaling and 3σ/µ variability for clock system is investigated in this work. An attempt to improve the slew of the clock system with un-buffered tree is made by redesigning the tapered H tree which exhibits better slew and robustness in sub-threshold regime.

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.

Hardware Designs for Security in Ultra-Low-Power IoT Systems: An Overview and Survey

The development of ultra-low-power (ULP) electronic devices has opened up opportunities for disruptive systems like the Internet of Things (IoT). The main concern is the security and privacy issues of the huge amount of personal, sensitive, or safety-related data being processed in these systems. Ensuring security in these ULP systems poses additional challenges than in computers, because of power and cost constraints and physical accessibility by attackers. To solve these problems, innovations in both software and hardware are needed. This article presents a survey of state-of-the-art hardware designs optimizing the tradeoffs between security, power, and costs (including design and manufacturing). The authors analyze the connections between hardware specs and system demands to bridge the gap between research conducted in different communities. They also identify open problems in designing future ULP secure hardware.

A 0.016 mm2 12 b $\Delta \Sigma $ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

The instrumentation systems for implantable brain–machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a $\Delta \Sigma $ SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0–2MASH topology. This configuration uses a specialized FIR window to decimate the $\Delta \Sigma $ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using $0.18\,\mu $ m CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm2 silicon footprint. Moreover, a 14fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2 Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications.

Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing

Power and energy reduction is of uttermost importance for applications with stringent power/energy budget such as ultralow power and energy-harvested systems. Aggressive voltage scaling and in particular near-threshold computing is a promising approach to reduce the power and energy consumption. However, reducing the supply voltage leads to drastic performance variation induced by process and runtime variation. Temperature variation is one of the major sources of performance variation. In this paper, we study the impact of temperature variation on the circuit behavior in the near-threshold voltage region and show that the ambient temperature has a huge impact on the metrics such as circuit delay, power, and energy consumption. We also propose a low-cost, ambient temperature-aware voltage scaling technique to reduce the unnecessary energy overhead caused by temperature variation. Simulation results show that our proposed approach reduces the energy consumption by more than 1.95×.

An Ultralow Power System on Chip for Automatic Sleep Staging

This paper presents an ultralow power system on chip (SoC) for automatic sleep staging using a single electroencephalogram (EEG) channel. The system integrates an analog front end for EEG data acquisition and a digital processor to extract spectral features from these data and classify them into one of the sleep stages. The digital processor consists of multiple blocks implementing an automatic sleep staging algorithm that uses a set of contextual decision trees controlled by a state machine. The processor is designed to stay in the idle mode at most times waking up only when computations are required. In addition, the mathematical operations are implemented in a way such that the number of datapath components needed is very small. The SoC is implemented in an AMS 0.18-μm CMOS technology and is powered using a single 1.25-V supply. Its power consumption is measured to be 575 μW, while its classification accuracy using real EEG data is 98.7%.