Ultra-low Power Systems Research Articles

An Analog Gabor Transform Using Sub-Threshold 180-nm CMOS Devices

The Gabor transform can be used to represent a signal in terms of a set of pseudo basis functions, allowing a signal to be split into parallel paths of a lower bandwidth. An analog Gabor transform using sub-threshold CMOS continuous time filters designed from time domain impulse responses is described. A novel method for designing low power gm-C filters using simple models of identical transconductors is used to specify the transistor sizes. Measured results show that the transform consumes 7 ¿W for an input signal bandwidth of 4 kHz, making it suitable for ultra low power systems.

Implantable ultra-low power DSP-based system for a miniature chemico-rheological biosensor

An active implantable chemico-rheological sensor including control electronics, a Digital Signal Processor (DSP) and an RF transceiver has been demonstrated. The ultra-low power system architecture achieves an energy per viscosity measurement of only 16.6mJ of which 56% are dedicated to the micro-rheometer, 40% to the transceiver, and 4% to the DSP. Four coins batteries with a capacity of 150J each (Energizer 376) enabled a life time of 28’500 cycles at 37°C. The System in Package (SiP) fits in a 8.4mm in diameter cylinder and hence is implantable. As this generic system is fully programmable, it may further control any biosensor or bioactuator.

A high-level clustering algorithm targeting dual V dd FPGAs

Recent advanced power optimizations deployed in commercial FPGAs, laid out a roadmap towards FPGA devices that can be integrated into ultra low power systems. In this article, we present a high-level design tool to support the process of mapping an application onto a FPGA device with dual supply voltages. Our main contribution in this paper is an algorithm, which creates voltage scaling ready clusters by utilizing the timing slack available in the designs. We propose to first create clusters of CLBs within a given CLB-level netlist. This clustering algorithm intends to group chains of CLBs possessing similar amounts of timing slack along their critical path together. Once these clusters are identified, they are placed onto respective V dd partitions on the device. We have evaluated different dual V dd fabrics and the potential gain in power consumption is explored. When a subset of the logic blocks on the device can be driven by low V dd levels (either with a dedicated low V dd supply or with a programmable selection between low and high V dd levels for these blocks) this affects placement and routing. As a result the maximum frequency of the designs may be affected. In order to evaluate the overall impact of creating voltage islands, we measured the Energy-Delay Product for our benchmark designs. We observed that the Energy-Delay product can be decreased by 26.9% when the placement of the designs into different voltage levels is guided by our clustering algorithm.