Ultra Low Power Supply Voltage Research Articles

Parallel Multilevel Cell STT-MRAMs for Optimized Area Energy and Read–Write Operations

Spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for the next generation embedded memory applications. The advent of a perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) device has made the STT-MRAM viable for low-power high-density on-chip memory architectures. However, intense research efforts are still required to optimize the single-level cell and multilevel cell (MLC) STT-MRAMs in terms of area, energy, and read–write operations at ultralow power supply voltages. In this paper, a parallel MLC (pMLC) STT-MRAM (20–50 nm) is proposed to provide smaller footprint area, energy efficient, and optimized read–write operations with very low failure probabilities at the supply voltage of 1 V. These designs utilize high- ${k}$ gate dielectric gate-all-around silicon nanowire-based vertical NMOS transistor as a switching device. The PMTJ device is modeled using Verilog-A. The HSPICE simulation results affirm the suitability of pMLC designs, e.g., 3-bit pMLC design exhibits, switching error probability much less than 10−9, and average write energy of <2 pJ with minimum cell-area at the pulsewidth of 10 ns.

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 $$\sigma $$ ? Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.

Effect of Total Ionizing Dose on a Bulk 130 nm Ring Oscillator Operating at Ultra-Low Power

Total ionizing dose experiments showed an increase in operating frequency (and therefore, power consumption) in bulk CMOS ring oscillators when operated at ultra-low power supply voltages. Combined-environment experiments showed the single-event susceptibility of ULP circuits increases with total dose exposure. To operate ULP circuits in a total dose environment and ensure there is little change in their circuit characteristics, the supply voltage should be greater than 400 mV.

PTAT Voltage Generator under Ultra Low Power Supply with Two Subthreshold MOSFETs between Rails

A proportional to absolute temperature voltage (PTAT Voltage) generator under ultra low power supply with MOSFETs operating in weak inversion region is proposed. The PTAT voltage generator is a necessary circuit for temperature sensor and bandgap reference circuit under low power supply in minimized CMOS analog integrated circuit. When two MOSFETs operating in weak inversion region are connected between rails, the PTAT voltage generator can be driven even under ultra low power supply voltage. As gate terminals are common in two MOSFETs connected in series and also bulk terminals are common, a gate to bulk voltage for MOS diode in a MOSFET is equal to that in another MOSFET. The proposed PTAT voltage generator operating under supply voltage from 0.2V to 1.8V with -70dB PSRR is fabricated with a standard 0.18μ m n-well CMOS technology and measured to investigate the basic principle. The measured characteristics of output voltage versus temperature fit to the theoretical ones deriving from design principle exactly.

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.

Time Resolved Photon Emission Processing Flow for IC Analysis

IC analysis can be facilitated using Time Resolved Photon Emission (TRE). Because recent technologies work at ultra low power supply voltages: <1V, background noise can mask commutation peaks thus biasing analyses. With a positive photon discrimination flow, signals can be extracted even below the noise level. However signal extraction depends on various parameters (e.g., bin size, cutoff frequency). WE have developed a photon discrimination technique to optimize these parameters. This technique is integrated into a generic method which takes advantage of static light emission acquisition for identifying switching transistors and which links TRE measurements to simulations for optimal IC diagnostics.