Ultra Low-k Research Articles

FEA Assisted Optimization of Bump Shear Test Method for Assessment of Back-End-of-Line Mechanical Integrity

An enhanced Cu pillar bump shear test (BST) method has been developed to quantify wafer level back-end-of-line (BEOL) mechanical integrity and assess the risk of white bump failure. First, three different types of failure mode in the BST and the one that corresponds to the white bump failure in which delamination occurs at an ultra-low-k (ULK) dielectric layer, were identified by studying the load-displacement data together with focused ion beam (FIB) and scanning electron microscopy (SEM) analysis. To find the reason for different failure modes in BST and the effects of BST conditions, first, the difference in the stress modes between the bump shear test and the assembly solder reflow process was compared using finite element analysis (FEA) stress simulations. Then, parametric studies on the bump shear angle and the bump shear height were performed to find the optimal conditions at which the BST stress modes best mimic those of the solder reflow. Based on these studies, special high Cu pillar bump test samples were built in order to apply the optimal shear height and angle condition. The new optimal BST method has shown to significantly increase the probability of ULK delamination failure mode and was shown to be in good agreement with reflow hammer test results. Also, the method was used to verify the effect of metal density as well as process and design changes. Finally, a machine learning based correlation for quantifying the pure BEOL integrity regardless of the bump and far-BEOL dimensions was developed for application of the method to various products.

Modification of Porous Ultralow-k Film by Vacuum Ultraviolet Emission

Modification of spin-on-deposited porous PMO (periodic mesoporous organosilica) ultralow-k (ULK) SiCOH films (k = 2.33) containing both methyl terminal and methylene bridging groups by vacuum ultraviolet (VUV) emission from Xe plasma is studied. The temporal evolution of chemical composition, internal defects, and morphological properties (pore structure transformation) is studied by using Fourier transform infrared spectroscopy, in situ laser ellipsometry, spectroscopic ellipsometry, ellipsometric porosimetry (EP), positron-annihilation lifetime spectroscopy (PALS), and Doppler broadening positron-annihilation spectroscopy. Application of the different advanced diagnostics allows making conclusions on the dynamics of the chemical composition and pore structure. The time frame of the VUV exposure in the current investigation can be divided into two phases. During the first short phase, film loses almost all of its surface methyl and matrix bridging groups. An increase of material porosity due to removal of methyl groups with simultaneous matrix shrinkage is found by in situ ellipsometry. The removal of bridging bonds leads to an increase of matrix intrinsic porosity. Nevertheless, when the treated material is exposed to the ambient air, the sizes of micro- and mesopores and pores interconnectivity decrease with the VUV exposure time according to PAS and EP data. The last is the result of the additional film shrinkage caused by atmosphere exposure. During the second phase the increase of mesopore size is detected by both EP and PAS. The increase of mesopore size goes all the time as it is expected from in situ ellipsometry, but it is masked by the air exposure.

Novel XPS Technique for Fluorocarbon Layer Evaluation on Nano-Scale Sicoh Sidewalls

Motivation: The Back End of Line (BEoL) in semiconductor industry uses carbon doped silicon oxides (SiCOH), also called ultra-low-k (ULK) or low-k dielectrics as insulating materials. During reactive ion etching (RIE) of those materials, fluorocarbon passivation layer is formed which controls the etch profile and the plasma induced damage of the material. The etch front of the dielectric is dynamically removed during etching. Due to anisotropic plasma the FC layer builds up differently on the trench sidewalls. Therefore the FC layer on trench sidewalls and the trench bottom should be quantified [i]. It is challenging to study the vertical sidewalls in a patterned film. This work aims to implement X-Ray Photoelectron Spectroscopy (XPS) technique to analyze the sidewalls of the etched film and quantify the buildup of passivating FC layer on the sidewalls in different etch recipes. Methodology: Dense SiCOH (k=2.75, open porosity=7%) with initial thickness of 160nm was deposited on 300mm Si wafers. The wafers were patterned using E-beam lithography. The pattern consists of parallel trench arrays of varying trench widths (50nm to 1500nm) and line widths (75nm to 125nm). Wafers were etched with C4F8/CF4/N2/Ar (Recipe_1) and CHF3/CF4 (Recipe_2) plasma in a Dual Frequency Capacitive Coupled Plasma (CCP) etch chamber. Post etch trench depth and critical dimension (CD) bias of the etched structures were measured using spectroscopic ellipsometry and critical dimension scanning electron microscopy (CDSEM) respectively. Each structures were then measured under XPS for the surface chemical composition.The XPS methodology is based on the mathematical separation of the photoelectron signal intensities of the three different surfaces of a trench, namely the Line Top, Trench Sidewalls and Trench Bottom[ii]. In a model-based approach, electron shadowing by the opposite trench sidewall is calculated using the measured geometry from ellipsometry and CDSEM. It assumes that every point surface on the sidewall emits electrons and only the electrons falling in the acceptance cone of XPS electron detector are counted which limits the conical opening to 60º inclined at 50º to sample surface normal (Fig.1a). Analysis depth of the sidewall varies with the trench width and the trench angle. A physical model is developed to calculate the sidewall analysis depth which is not shadowed by the opposite sidewall (Fig.1b).The layout contains various pitch size which constitute different area ratios of Line Top, Trench Sidewalls and Trench Bottom. In order to find the chemical composition of each surfaces independent of their visible areas, the system of linear equations is solved using Multiple Linear Regression method to find out the signal intensity per unit area from all three surfaces, assuming that each surface composition remains constant across every pitch size. Comparison of the signal intensity per unit area indicates amount of sidewall passivation w.r.t trench bottom. As an additional verification to the methodology and electron shadowing, parallel angle resolved XPS (pAR-XPS) have been carried out at the same structure to find out the variation in sidewall contributions with different angles. Observation: Recipe_1 is highly passivating (C4F8 presence) but directional (high Ar content), therefore shows less deposition of FC layer on the sidewalls compared to line top and trench bottom, shown by the least F1s F-C and C1s C-Fx (x=1:3) intensity but high FC layer deposition on flat surfaces with remaining photoresist adding more carbon and nitrogen to line top than trench bottom (Fig.1c).Recipe_2 shows lower passivation (CHF3 presence) and anisotropy (No Ar) than Recipe_1, therefore lower carbon is seen on line top and trench bottom compared to Recipe_1, but a thicker FC layer on sidewalls. In both the recipes sidewalls and trench bottom shows similar level of Si2p Si-O and O1s O-Si signal intensities but only differ in their FC layer buildup due to different plasma chemistry. Line top with higher carbon content has lesser intensity of Si2p Si-O and O1s O-Si than the other with thinner FC layer buildup. Conclusion: The results confirm that the physical model is capable of separating the signal intensities from the three surfaces through which the FC layer on each surfaces have been accurately predicted. Therefore the normal mode XPS technique can be utilized to gain insight into the chemical composition of sidewalls. Acknowledgement: This work was funded via subcontract from Globalfoundries Dresden within the framework Important Project of Common European Interest (IPCEI) by the Federal Ministry for Economics and Energy and by the State of Saxony.

Introduction of Laser Pi-Grooving as Breakthrough Solution to Enhance die Strength of 40 nm ulow-k CMOS Silicon Technology during Wafer Saw Process

Nowadays, semiconductors and electronics are becoming part of our everyday activities. As the Integrated circuits become more useful to people, it also requires more function, which contain more complex and compact components. Aligned to this package requirement, the more challenging it become to package development as Silicon technology becomes more critical and complex from bare silicon to conventional MOS technology to Ultra Low-K, which requires a different strategy. The new process development in the Semiconductor industry is a necessity to cope up with these new technologies. Low-k devices always pose a big challenge in achieving good dicing quality. This is because of the weak mechanical properties of the low-k dielectric material used. Mechanical Sawing is the most popular cutting method for silicon, but with Ultra low-K technology, using mechanical sawing will lead to various sawing defects such as chippings and delamination [1,2]. These leads to the introduction of Laser Grooving to get rid of these dilemmas. Laser grooving uses heat to eradicate metals on this very thin metal wafer dicing saw streets in preparation for wafer saw process to prevent topside chippings and delamination/metal peel off [3]. These defects are not acceptable especially since the product application is a chip card. Since chip cards must be flexible and durable, they require higher die and package strength to serve its purpose. To achieve such package requirement, different method was evaluated such as standard mechanical dicing, standard Laser Grooving and the PI laser groove. 
 The paper will discuss how we were able to achieve the quality requirement for Ultra Low-K and at the same time eliminating top reject contributor during startup of this device.

Investigation of Fluoro-Carbon Layer on Dense Sicoh Formed during CF4 and CF4/C4F6 Based Continuous Wave Plasma Etch

Motivation: Plasma etching of low-k and ultra low-k (ULK) dielectric materials have seen a tremendous growth in deep nanoscale applications. Fluorocarbon based gases are the forerunners in etching low-k dielectrics as they are the F suppliers necessary to remove Si and C from SiCOH material. Different FC gases in combination with the additive gases contribute differently to the etch behavior of SiCOH due to differing reaction chemistry and formation of Fluorocarbon layer as an interfacial layer between plasma front and dielectric front [i]. Due to dynamic formation and etching of FC Layer happening at the dielectric surface, understanding FC layer properties in each gas plasma is the starting step to control etch rate and plasma induced damage in Low-k dielectrics. This paper aims to study and compare FC layer deposition by different gases grouped into CF4 and CF4/C4F6 family with N2, O2 and H2 as additive gases in each group. FC layer thickness, etch rate, optical properties of etched SiCOH and chemical composition of the FC layer by different plasma treatments have been presented in this work. Methodology: Dense SiCOH (k=2.75 and Open Porosity: 7%) with initial thickness of 157±3nm is deposited on 300mm Si Wafer with a thin SiO2 adhesion layer in between. These wafers are blanket etched in a commercial etch chamber with the given gas combinations (CF4, CF4/N2, CF4/O2, CF4/H2; CF4/C4F6, CF4/C4F6/N2, CF4/C4F6/O2, CF4/C4F6/H2) for same amount of time, total gas flow rate, similar power, pressure and temperature settings.Post Etch blanket wafers are subjected to various in-line and off-line metrology tools. In-line spectroscopic ellipsometer is used to model complex refractive index and thickness of individual layers. Tauc-Lorentz model best describes the FC layer whereas Cauchy model describes the dielectric [ii]. In-line XPS was carried out to probe the surface of FC layer and gain chemical information. Furthermore depth profile of etched layer is carried out by sputtering the surface with low power Ar ions to study variations in chemical composition with the layer depth. SEM is used to see the cross section profile and verify the results from above method Observation: Thickness evaluation from the dispersion models shows that the CF4 group has higher etch rate and lower FC layer thickness compared to CF4/C4F6 group. C4F6 has higher polymerization ability by the virtue of its lower F/C ratio. Amongst each group, Oxygen as additive gas shows the highest etch rate and least FC thickness followed by Nitrogen whereas Hydrogen has least etch rate but highest FC layer thickness. Under given etch conditions with CF4/C4F6/H2 plasma, deposition rate was higher than etching rate leading to stack growth (Fig.1a). Hydrogen supports polymerization by scavenging Fluorine away and aids in thicker FC films.XPS chemical composition shows Fluorine diffusion through FC layer into the dielectric layer bringing changes to its pristine structure. This affects Carbon% across the etched dielectric thickness (Fig.1b). Thicker the FC layer is, closer is the Carbon % to pristine SiCOH. Presence of surficial Nitrogen in the nitrogen containing plasmas shows nitrogen reacts with SiCOH Carbon, forms CN compounds and increases the etch rate. FC layer shows presence of CF3 radicals on the surface and decrease fast with the depth, followed by CF2 radicals. CF radicals are in larger quantity and are present deepest into the FC Layer. Presence of polymerized C-C and C-CFx bonds increases with the FC Layer depth and offset with increase of C-Si bond near the SiCOH interface. Conclusion: This paper shows comparison of Etch Rate and FC layer thickness during SiCOH etch using different gas combinations in the CCP plasma chamber. Thickness correlation between ellipsometric model data and XPS depth profile followed by SEM cross section measurement of layer thickness point towards the correctness of dispersion models for each layer. These models can be used for quick inline post etch metrology useful for process control. O2 containing plasmas are too aggressive on the dielectric with negligible FC layer formation, while H2 containing plasmas are less damaging but exhibit very small etch rate. CF4/C4F6/N2 plasma is the optimum combination for Low-k dielectric etch amongst other combinations in terms of desired etch rate and lower reduction in Carbon %. Relative concentration and penetration depth of different CFx radicals in FC film suggests its influence on film structure.

On the relationship between SiF4 plasma species and sample properties in ultra low-k etching processes

The temporal behavior of the molecular etching product SiF4 in fluorocarbon-based plasmas used for the dry etching of ultra low-k (ULK) materials has been brought into connection with the polymer deposition on the surface during plasma treatment within the scope of this work. For this purpose, time-resolved measurements of the density of SiF4 have been performed by quantum cascade laser absorption spectroscopy. A quantification of the non-linear time dependence was achieved by its characterization via a time constant of the decreasing SiF4 density over the process time. The time constant predicts how fast the stationary SiF4 density is reached. The higher the time constant is, the thicker the polymer film on top of the treated ultra low-k surface. A correlation between the time constant and the ULK damage was also found. ULK damage and polymer deposition were proven by Variable Angle Spectroscopic Ellipsometry and X-ray Photoelectron Spectroscopy. In summary, the observed decay of the etching product concentration over process time is caused by the suppressed desorption of the SiF4 molecules due to a more dominant adsorption of polymers.

Plasma Induced Damage Reduction of Ultra Low-k Dielectric by Using Source Pulsed Plasma Etching for Next BEOL Interconnect Manufacturing

In order to reduce the interconnect resistance and capacitance (RC) time delay of a semiconductor integrated circuit, a more porous dielectric material is used in recent interconnection for lower dielectric constant. However, it is difficult to use highly porous low-k dielectric materials at the narrow pitch because it is easily damaged during the plasma etching processes. In this study, as one of the plasma induced damage reduction methods in the etching of porous low-k dielectric, RF pulsed plasma methods have been investigated by using a dual frequency capacitively coupled plasma etching system. RF pulsed plasmas generated more polymerizing species and less UV compared to continuous wave plasmas and showed reduced damaged layer compared to the conventional continuous wave plasma etching. Porous SiCOH dielectric patterned with a TiN hard mask was etched using the RF pulsed plasmas and the results showed more anisotropic etching profiles with less sidewall damages, which was estimated by the thickness loss of sidewall low-k material after dipping into a diluted HF solution. Therefore, it is believed that the RF pulsed plasma etching process of ultra low-k dielectric materials can improve the RC time delay related to plasma damage for the next interconnect manufacturing technology.

Etch Damage Reduction of Ultra Low-k Dielectric by Using Pulsed Plasmas

To reduce interconnect resistance and capacitance (RC) time delay of semiconductor integrated circuit, the dielectric material with more porosity is used in recent interconnection for lower dielectric constant. However, it is difficult to use highly porous low-k dielectric materials at the narrow pitch because it is easily damaged during the plasma etching processes. In this study, as one of the plasma induced damage reduction methods in the etching of porous low-k dielectric using C4F8-based gases, RF pulsed plasma methods have been investigated by using a dual frequency capacitively coupled plasma etch system. RF pulsed plasmas generated higher carbon-rich radicals in the plasma and less charging effect on the dielectric material surface compared to continuous wave plasmas and, therefore, showed a reduced damaged layer compared to the conventional continuous wave plasma etching. Porous SiCOH dielectric with a patterned TiN hard mask was etched using the RF pulsed plasmas and the results showed more anisotropic etching profiles with less sidewall damages. Therefore, it is believed that the RF pulsed plasma etching process of ultra low-k dielectric materials can improve the RC delay related with plasma damage for the next interconnect technology.

Low-k dielectric etch challenges at the 7 nm logic node and beyond: Continuous-wave versus quasiatomic layer plasma etching performance review

For logic nodes of 7 nm and beyond, back-end-of-line (BEOL) trench patterns have a critical pitch of less than 40 nm, directly affecting the plasma etch process window of the dual damascene etch process. Feature size dependent etch depth (reactive ion etch, RIE lag), hard mask selectivity, and ultra-low-k (ULK) damage have become significant challenges that must be overcome in order to meet target device performance. Recently, atomic layer etching has been used to widen the plasma etch process window in terms of selectivity and process control [S. Sherpa, P. L. F. Ventzek, and A. Ranjan, J. Vac. Sci. Technol. A 35, 05C310 (2017); T. Tsutsumi, H. Kondo, M. Hori, M. Zaitsu, A. Kobayashi, T. Nozawa, and N. Kobayashi, J. Vac. Sci. Technol. A 35, 01A103 (2017)]. In this work, the impact of a quasiatomic layer etch (QALE) process, a conventional continuous wave plasma, and a pulsed plasma process on ULK materials were investigated to determine the benefits of an ALE process approach for BEOL etching. Both blanket ULK film and patterned ULK samples were used for this study. The ULK etch damage from each process was characterized using Fourier transform infrared spectroscopy and x-ray photoelectron spectroscopy on three different ULK films. From patterned samples, it was determined that QALE could be used to successfully suppress RIE lag in low-k materials at advanced pitches, while keeping low-k damage to a minimum. In addition, the QALE technique showed improved hard mask selectivity and resulted in lower line edge pattern roughness. Based on this study, the authors concluded that QALE is a powerful plasma etch method to overcome BEOL etch challenges at advanced pitches.

Mechanical integrity of nano-interconnects as brittle-matrix nano-composites

In this study, the mechanical integrity of advanced multilayer nano-interconnects, as metal/dielectric nano-composites, was investigated using a combination of analytical modelling, computational mechanics and experiments. A method for fast derivation of the effective orthotropic elastic moduli of complex multilayer nano-interconnects was demonstrated and corroborated using finite element modelling (FEM). Subsequently, the effective elastic properties were employed for homogenization and course-graining in computational fracture mechanics models. This allowed the model development and simulation time to be reduced drastically and also enabled the global delamination behavior in nano-interconnects to be predicted consistent with experimental results. The study identified the via layers integrated with ultra low-k (ULK) dielectrics as the delamination prone layers. Particularly, failure analysis following exposure to bump shear tests revealed that the via layer adjacent to the top stiff layers was the dominant fracture path. By using analytical and computational mechanics it is shown that the elasticity mismatch between the soft intermediate group of layers and the stiff top group of layers dictates this delamination mode. Detailed FE modeling, showed that when vias are uniformly distributed, increasing the via density by only a few percent will increase the mechanical integrity drastically. Delamination experiments revealed a statistically significant increase of critical fracture energy (Gc) of ULK dielectric films when their thickness is reduced. Thus, reducing the thickness of the via layers, will also increase their effective Gc. However, analytical modelling together with experiments indicate that this trend will apply down to an optimal via layer thickness of approximately 30 nm where the Gc is predicted to reach its theoretical maximum in the case of organosilicate glass ULK (OSG 2.55).

Damage and etching of ultra low-k materials in fluorocarbon plasma at lowered temperatures

SiOCH ULK films with k-value from 2.5 to 2.1 and porosity from 24 to 40% were etched in CHF3, CHF3 + Ar, CF4 and CF4 + Ar plasmas at +15…−120 °C with and without bias being applied. It was shown that the presence of Ar in gas mixture can significantly increase the damage of unetched ultra low-k (ULK) material (at sidewalls) due to the removal of −CH3 groups from the film by VUV photons. It was also shown that etching and damage of the sidewalls by F atoms can be partially prevented by lowering the temperature of the sample.

Impact of Alkaline Solutions on Via Resistance Reduction and Critical Dimension (CD) Control for Sub-10 Nm Technology Nodes

The continued scaling for back-end-of-line (BEOL) for the sub-10 nm node poses significant challenges due to the shrinkage in dimensions and reduced Cu volume. Specifically for via, a clean interface between the underlying metal (Cu, Co) and Ta/TaN liner is required to reduce additional resistance-capacitance (RC) delays. Traditionally, fluoride based wet chemical systems are used to remove CuO x and post etch residues from the ultra-low k (ULK) dielectric sidewalls [1]. However, as the critical dimensions (CD) of BEOL integrated structures continue to shrink, the loss of RIE damaged low k dielectric material due to dilute HF (dHF) processing becomes a major concern. Furthermore, as Co metallization processes are being explored in interconnect structures, this necessitates an alternative to fluoride based solutions due to their incompatibility [2]. In this work, we are investigating an alternative alkaline based solutions with the addition of surfactants to prevent Cu/Co corrosion while effectively cleaning post etch residues with minimal CD loss. Some of the key parameters studied include solution concentration, oxygen levels, temperature and pH. Careful consideration was taken to adjust the solution pH by controlling the inhibitor concentration to enable Cu surface passivation while still effectively removing post etch residue (PER). As a first step, the Cu etch rates at a fixed alkaline solution concentration were measured using X-ray fluorescence (XRF) technique. Without corrosion inhibitor, Cu etch rates of 5 Å/min and 10 Å/min, respectively were measured at room temperature (RT) and 60 °C solution temperature. A significant reduction in etch rates of less than 2 Å/min was measured with the optimized inhibitor concentration in the alkaline solutions. There was no measurable change in ULK thickness for the pristine and damaged ULK films at RT, while approximately 5 Å loss at 60 °C was measured for the pristine film. Based on these results, optimized solution parameters such as concentrations, temperature, pH and process time, were developed. A transmission electron microscope (TEM) image of the metallized via structure is presented in Figure 1. It demonstrates that via structures remain intact with a continuous metal fill and no significant removal of the exposed underlying metal layer from the alkaline based cleans process. Additionally, the impact of cleaning was electrically evaluated by measuring resistance and yield using a metal-hardmask-trench-first-via-last (MHTFVL) scheme. Results indicate equivalence in comb-serpentine and via chain yields for the optimized alkaline solution compared to the dHF process. The electrical results for the normalized isolated via chain resistance values were within ~5% of the dHF baseline as shown in Figure 2. This demonstrates the ability of the alkaline based cleaning process to remove CuO x from the bottom of the via to achieve necessary inter-level resistance targets. In conclusion, alkaline based chemistries with the addition of surfactants are a suitable alternative to dHF based cleaning methods to remove RIE based polymer residues from high aspect ratio trench and via structures while maintaining stringent CD targets for sub-10 nm technology nodes. Acknowledgement: This work was performed by the Alliance Teams at various IBM and GLOBALFOUNDRIES Research and Development Facilities References [1] B. Peethala, F.W. Mont, S. Mollis, R. Knarr, B. L’lherron, C. Labelle, D. Canaperi, S. Siddiqui, Microelectronic Eng., 161, 98-103 (2016). [2] V. Kamineni et al., “Tungsten and Cobalt Metallization: A Material Study for MOL Local Interconnects”, International Interconnect Technology Conference (IITC), May 23 - 26 '2016, San Jose, California, USA. Figure 1

Via Bottom Profile Optimization in All-in-One Etch with Double Patterning Scheme

—In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Metal Hard-Mask (MHM) All-In-One (AIO) etch is used to define smaller via and trench. The bottom profile of via is critical for via connectivity and RC delay. Tapered via bottom profile means smaller contact area with lower metal which means larger via contact resistance and degradation of chip interconnect performance. The bottom profile of via may probably become tapered when it enters Etch Stop Layer (ESL) or when the plasma touches lower Cu layer. In this paper, we will explain the reason of tapered via bottom profile and several ways to solve this problem. Keywords—AIO etch; Via bottom taper profile; ESL; Cu exposure; Metal capping layer; Introduction—In current LELE double patterning scheme, the partial via (PV) is firstly formed in 1st mask. Then the second PV is formed in 2nd mask, following by one in-situ ash which will remove PR tri-layer film. Then AIO etch will form via bottom and hard mask defined trench pattern at one etch process synchronously. MHM pattern is also defined by LELE double patterning before PV etch. The process sequence is briefly depicted in Fig.1. In our process, via is self-aligned by MHM for photo lithography reaches its limit on via. After photography critical dimension (CD) is quite large, via CD is shrunk during tri-layer etch process. After shrinking, Via CD is still larger than line CD. Therefore, we use self-aligned via (SAV) to confine via in MHM open area to ensure final VBD and TDDB performance acceptable. In this scheme, we should ensure MHM selectivity during whole etch process to let it not be etched through. Porous ultra-low-k (ULK) is introduced to reduce interconnect RC delay [1]. The etch stop layer (ESL) is introduced to balance different patterns’ loading after PV and trench etch. Then we used a LRM step to open ESL and touch lower Cu layer. However, we found the via bottom profile inside ESL is usually tapered. The tapered via profile into ESL could result in decreased contact area to lower metal Cu which is critical to final RC value. The plasma etch rate in ESL is always relatively slow to make sure the former PV and trench etch step can stop on it. For the practical ULK and ESL film thickness in advanced technology node, the selectivity ULK to ESL should be at least 5 to ensure 80-90% percentage of trench depth is etched by trench etch step, and the following ESL opening step just remove the little trench depth remaining [2]. In final Liner Remove (LRM) step, the etch rate cannot be so fast, meanwhile the etch rate (ER) will be slower after Cu exposure. In fluorocarbon plasma with oxygen, oxygen captures carbon to form C-O bond and control the polymer generation. Such ER change is induced by the reduction of oxygen ion after Cu exposure which will affect the total etch performance to form tapered via bottom profile. In this paper, tradition way to change plasma condition, the change of ESL and the introduction of lower metal capping layer will be used to solve via bottom tapered issue.

Surface-Localized Sealing of Porous Ultralow-k Dielectric Films with Ultrathin (

Semiconductor integrated circuit chip industries have been striving to introduce porous ultralow-k (ULK) dielectrics into the multilevel interconnection process in order to improve their chip operation speed by reducing capacitance along the signal path. To date, however, highly porous ULK dielectrics (porosity >40%, dielectric constant (k) <2.4) have not been successfully adopted in real devices because the porous nature causes many serious problems, including noncontinuous barrier deposition, penetration of the barrier metal, and reliability issues. Here, a method that allows porous ULK dielectrics to be successfully used with a multilevel interconnection scheme is presented. The surface of the porous ULK dielectric film (k = 2.0, porosity ∼47%) could be completely sealed by a thin (<2 nm) polymer deposited by a multistep initiated chemical vapor deposition (iCVD) process. Using the iCVD process, a thin pore-sealing layer was localized only to the surface of the porous ULK dielectric film, which could minimize the increase of k; the final effective k was less than 2.2, and the penetration of metal barrier precursors into the dielectric film was completely blocked. The pore-sealed ULK dielectric film also exhibited excellent long-term reliability comparable to a dense low-k dielectric film.

Film deposition and UV curing process impact on ultralow-k dielectric for high performance Cu interconnects

Ultralow-k (ULK) film deposition and UV curing process were studied to explore the effects on the mechanical, electrical and chemical properties of ULK dielectrics. UV curing process plays an important role to enhance the Young’s modulus (mechanical performance) by increasing the formation of –Si–O–Si– cross-linking, and ULK film deposition with low film shrinkage ratio can form a robust porous SiOCH to avoid following integration process-induced damage on ULK dielectrics and also improve the device reliability performance significantly.

Tween-80 based ultra low-k (ULK) mesoporous films

The non-ionic surfactant polysorbate 80 (Tween-80) based single step HF assisted mesoporous low-k films were synthesized by using sol–gel spin coating technique. The obtained films were annealed at 150 °C for 1 h to remove the added porogen and the pore solvents. Film thickness and refractive index were measured by spectral ellipsometry and changes in chemical compositions were investigated by using FTIR spectroscopy. The formation of SiO2 in film matrix and incorporation of low polar bonds like F and C were confirmed from obtained FTIR spectra. The porous nature of deposited film was confirmed from FE-SEM micrograph and the measured average pore diameter of mesopores was found to be 16.54 nm. The highest porosity percentage of 60.74% was obtained for the annealed sample deposited with 1 ml of Tween-80 in coating solution. The measured RMS roughness of the samples before and after annealing was observed to be increased from 0.029 to 0.079 nm. The lowest dielectric constant extracted from C–V curve measurement is of 1.06. These obtained mesoporous films with lower k value of 1.06 may be a suitable candidate as interlayer dielectric (ILD) for back end of line (BEOL) in CMOS technology.

A novel tri-layer nanoindentation method to measure the mechanical properties of a porous brittle ultra-low-k dielectric thin film

The mechanical properties of two porous ultra-low-k (ULK) dielectric thin films (porous carbon-doped silicon dioxide (pSiCOH); and octamethylcyclotetrasiloxane (OMCTS)) were measured by nanoindentation. Since a direct contact of a nanoindentation tip with a thin and brittle ULK film will likely induce damage to the film and thus alters its mechanical response, the mechanical properties measured from direct nanoindentation on an ULK film do not necessarily represent the behavior of an ULK thin film in service condition. To circumvent this difficulty, a novel tri-layer configuration was used for sample preparation. In this method, a thin layer of tetraethyl orthosilicate (TEOS) silica was deposited on an ULK thin film to protect it from direct contact with a nanoindenter tip. A nanoindenter tip was in contact with TEOS coating on the layered film in nanoindentation, and the collected data was subsequently analyzed by finite element analysis. The Ogden hyperfoam model was used as the constitutive law for the ULK film in simulations, and found to be appropriate. Results indicate that the linear elastic model is only applicable for very small strains. At large strains the ULK films show nonlinear behavior due to densification of the porous ULK material under compaction. The moduli for the pSiCOH and OMCTS dielectric films were determined as 2.6 GPa and 5.2 GPa, respectively.

Minimize Electron Beam Damage during Characterization of Carbon-Depletion in Ultra Low-K Dielectric Materials by STEM EELS Elemental Mapping

Minimize Electron Beam Damage during Characterization of Carbon-Depletion in Ultra Low-K Dielectric Materials by STEM EELS Elemental Mapping

Application of STEM EELS Quantification Relative Compositional Ratio Mapping to Characterize SiCOH - Ultra Low-k Dielectric Materials in Si-based Devices

Application of STEM EELS Quantification Relative Compositional Ratio Mapping to Characterize SiCOH - Ultra Low-k Dielectric Materials in Si-based Devices

An Assessment of Risk of Fracture During Wirebond Over Active Circuits on ULK Dies

Mechanical integrity of the dielectric stack is challenged by the trend toward porous, lower dielectric constant interlayer dielectric (ILD) materials. During copper wirebonding over active circuits, the fracture of ultralow-k (ULK) dielectrics is a significant reliability challenge due to both the impact load and the high ultrasonic energy transmitted to the ILD stack. Thus, there is a need to assess the propensity of the ILD to fracture under the wirebonding process conditions. In this paper, a numerical investigation of the risk of fracture in ULK dies due to the Cu wirebonding process is presented. A recently developed computational technique for modeling cracks using behavioral approximations built directly on the geometrical model (enriched isogeometric analysis), as opposed to the analysis of a meshed geometry, is adopted to model damage in the ULK stacks. The cohesive damage induced in the ILD stack during the process steps, which is a measure of the risk of crack initiation, is used as an indicator of the reliability risk. The damage accumulation during the Cu wirebonding process is estimated to identify weak interfaces and potential sites for crack nucleation as well as damage nucleation patterns. Furthermore, the critical process condition at which crack nucleation is likely is identified by analyzing the damage induced during the impact and ultrasonic excitation stages. Also, representative ILD stack designs with varying Cu percentage are compared to assess the relative risk of fracture.