Ultra Large Scale Integrated Circuits Research Articles

Importance of Thermophysical Properties of Thin Films in Ultra-Large-Scale Integrated Circuits and Beyond

Ultralarge-scale integrated circuits (ULSICs) are fabricated in a single crystal of silicon using submicron device structures arrayed in two dimensions, which are interconnected in the third dimension with multilevel metallizations. The latter use several alternating layers of metal and dielectric films. Currently, four-level metallizations are used in large volume ULSIC manufacturing. As the technologies advance in ULSICs and beyond, four-level metallizations are expected to increase to six-level and higher. In three-dimensional ICs (3-D ICs) and ultraperformance ICs (UPICs), in which active devices are also fabricated in the third dimension in addition to the interconnects, the total number of semiconductor, dielectric, and metal films increases significantly. The thermophysical properties of all of these films play an ever-increasing role in the overall yield, reliability, and chip size of the ICs. The thermophysical properties considered in this paper are the thermal conductivity κ and the stress σ and its variations on thermal cycling, of the SiO2 films only. Data for these parameters are shown, with comments on their impact on the reliability of the ICs, and the role of Umklapp and point defect scattering mechanisms on the κ of thin films is discussed. The thermophysical properties not only are important in the current ULSICs for enhanced performance and reliability, but are even more crucial for the design and manufacturing of the next generation ICs like 3-D ICs and UPICs.

Low dielectric constant materials and methods for interlayer dielectric films in ultralarge-scale integrated circuit multilevel interconnections

This paper reviews low dielectric constant materials for interlayer dielectric films in ultralarge-scale integrated circuit (ULSI) multilevel interconnections. The trends of ULSIs in the last decade were briefly described first. Then, the requirements for interlayer dielectric film properties and their formation techniques were explained. They are: (1) a low dielectric constant, (2) a surface planarity, (3) a gap-filling capability, and (4) a low residual stress. In contrast with the requirements, the interlayer dielectric films and related technologies developed in the last decade were reviewed. In the requirements, the low dielectric constant materials are strongly required because the device performance has been limited by signal propagation time and cross-talk in the multilevel interconnections. Furthermore, the low dielectric constant is also required for reduction of power consumption in ULSI operation. Finally, the low dielectric constant materials were summarized, and future trends of the low dielectric constant interlayer dielectric film technologies are discussed.

TiN Diffusion Barrier Formation by Pulsed Source Chemical Vapor Deposition method

ABSTRACTTiN film is applied as a diffusion barrier and an adhesion promotion layer in the ultralarge scale integrated circuit (ULSI) devices. These TiN thin films are usually deposited by sputtering and chemical vapor deposition (CVD) methods. The CVD method is now studied intensively due to its satisfiable step coverage and compatibility with current device fabrication process. There are several different CVD methods already proposed such as LPCVD, MOCVD and PECVD. These proposed CVD methods have many disadvantages such as impurity incorporation and particle generation due to gas phase reactions between source and reactant gases. To solve these problems, we propose a new CVD method to reduce impurities and particles which is the pulsed source chemical vapor deposition (PS-CVD) method. In this method, the source, reactant and purge gases are introduced into reaction chamber, separately. TiN films are deposited using TiCl4, NH3 and Ar by alternately introducing into reaction chamber. In detail, TiCl4 source is introduced and adsorbed on Si substrate and then Ar gas purges this source gas. Continuously, NH3 gas in supplied into reaction chamber and adsorbed on the Ti-adsorbed Si substrate and then Ar gas is again introduced to purge NH3 gas. These four steps are one cycle. The main variables in this experiment are source pulse time, source purge time, reactant pulse time, reactant purge time, and so on. The deposition characteristics are also different depending on substrate temperatures. Above the thermal decomposition temperatures, the film thickness is a function of the source pulse time like conventional CVD. Below the thermal decomposition temperatures, the film thickness is saturated and exhibits a constant value in this temperature range. The TiN film thickness depends only on the number of deposition cycle. The process window were determined by experimentally in this temperature range. Process variables were established, and then TiN films were deposited. The characteristics of this TiN diffusion barrier were analyzed. The surface microroughness, the chemical composition and contaminant contents were measured by AFM, SEM and AES. A crystal structure and the phase identification were performed with using XRD and the sheet resistance was measured by a four point probe. These results will be discussed and compared with the results of TiN formed by sputtered and conventional CVD methods.

The Impacts of Back-End High Temperature Thermal Treatments on the Characteristics and Gate Oxide Reliability of Thin Film Transistor in Ultra Large Scale Integrated Circuit Process

The impacts of the two major high temperature treatments on the characteristics of thin film transistors (TFT's) in the back-end process of ultra large scale integrated circuit (ULSI) technology have been investigated. TFT's without any high temperature treatment show poor characteristics. High temperature furnace annealing and rapid thermal annealing (RTA) which are performed for boron phosphorous tetra ethyl ortho silicate (BPTEOS) planarization can improve the characteristics of low temperature recrystallized TFT. Then, the technologies used for contact annealing result significant difference on the characteristics of TFT's. High temperature furnace contact annealing can still greatly improve the characteristics of TFT's. However, after furnace annealing for BPTEOS planarization, RTA contact annealing deteriorates the characteristics of TFT. High temperature furnace annealing for BPTEOS planarization improves the charge to breakdown (Q bd) value of the gate oxide of TFT and so does the furnace contact annealing. However, RTA contact annealing performed after the furnace planarization flow deteriorates that of the gate oxide.

Deposition and surface modification of SiOf films with low dielectric constant

Low dielectric constant fluorine-doped silicon dioxide (SiOF) films were deposited using electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECRPECVD) with SiF4 and O2 as source gases. The effect of fluorine addition on the dielectric properties of the film as a function of the SiF4/O2 gas flow ratio is described in this paper. Also, the effect of post-plasma treatment on the moisture absorption of SiOF films for IMD materials in multilevel interconnections of ultra-large scale integrated circuits (ULSIs) was investigated. The SiOF film deposited at an SiF4/O2 gas flow ratio of 1.0 exhibited a fluorine content of 11.8 at.% and a dielectric constant of 3.14. When the duration time of post-plasma treatment increased, the following results were obtained: The etch rate of SiOF films decreased from 80 A/sec to 10 A/sec, and surface roughness of the plasma-treated SiOF films increased in relation to the ion bombardment effect of the plasma. The refractive index and relative dielectric constant increased from 1.391 to 1.461 and from 3.14 to 3. 90, respectively, due to the changes of surface chemistry in post-plasma treatment. The leakage current density of SiOF films prepared by ECRPECVD using SiF4 and O2 was less than 1 x 10-9 A/cm2 and the breakdown field strength increased from 3.5 MV/cm to 8 MV/cm.

Low dielectric constant film formation by oxygen-radical polymerization of laser-evaporated siloxane

Polysiloxane thin films were proposed as low dielectric constant interlayer dielectrics for multilevel interconnection of ultralarge scale integration circuits. The films were prepared using oxygen-radical polymerization of siloxane oligomers. A variety of siloxane oligomers were thermally produced by the decomposition of polysiloxane bulk target using CO2 laser irradiation. Oxygen radicals generated by a remote microwave O2 plasma were injected into the vacuum chamber during film deposition. The films deposited with the oxygen radical injection were transformed from polysiloxane to carbon-deficient silicon oxide with increase of substrate temperature as confirmed by x-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy analyses. At a CO2 laser power of 10 W, an O2 pressure of 50 mTorr, a microwave power of 100 W, and a substrate temperature of 100 °C, the dielectric constant of the polysiloxane film was 2.0.

EBIC investigation of defects in SOI materials using a Schottky diode and buried oxide capacitor

Silicon-on-insulator (SOI) is a promising technology for the fabrication of ultra large scale integration circuits as thin silicon layers of good crystalline quality are now available which permit substantial enhancements of device performance. However, the fabrication of ultra thin films suitable for CMOS applications often reveals some crystal defects which must be characterised to understand their consequences on device performances. Such defects were already extensively studied from a crystal point of view using preferential etching techniques. In this work, the non-destructive electron beam induced conductivity (EBIC) technique was successfully used to study dislocations and stacking faults in SOI films obtained by direct bonding. The presence of a buried oxide in the SOI structure prevented any direct current path between the collection junction formed on the active layer and the back ohmic contact. It is shown that collection using a Schottky junction in series with the buried oxide capacitor yields a differentiation of the EBIC signal. The latter may be digitally integrated to retrieve the image with a substantially improved signal over noise ( S/N) ratio. The variation of the EBIC signal as a function of the scanning rate was also investigated. This technique permitted the observation of stacking faults and dislocations in the active layer simultaneously with defects in the buried oxide and/or at the silicon-oxide interface.

Synthesis of Ultra-thin stacked oxides using low pressure single furnace cluster process

ABSTRACTThis work describes the development of a new grow-deposit-grow cluster process to grow ultra-thin stacked oxides. Two approaches for stacked oxide synthesis are discussed, namely thermal and chemical stacked oxides. Fabrication of chemical stacked oxide involves forming the first grown layer chemically after pre-gate cleaning, subsequent deposition of a TEOS-SiO2 layer and final densification/oxidation in a single low pressure (LP) furnace operation. In comparison, all three steps for thermal stacked oxide are accomplished by the LP cluster operation. Both processes offer the advantages of reduced cycle time and higher throughput to the stacked gate technology that produces superior Si/SiO2 interfaces and exhibits higher resistance to plasma-damage during ultra large scale integrated circuit (ULSI) processing. The quality and electrical characteristics of the stacked oxides are discussed.

Computer Simulation of Stress Induced Dislocation Multiplication in Large-Diameter Silicon Wafer in High-Temperature Device Processing

The occurence of slip bands due to stresses in large-diameter Czochralski-grown silicon (Si) wafers was studied with computer simulation to maintain them dislocation-free in ultra-large-scale-integrated-circuits (ULSIs) manufacturing. Two types of stresses induced in the circular wafers are investigated; thermal stress originated either in radial temperature variation or in gravitational stress due to the bending moment caused by the wafer's weight itself. Since the advent of 200-mm-dia wafer era for devices, slip bands generated by the gravitational stress were discovered, extending from the point jig as elongated slippages along the directions, in addition to those due to thermal stresses. On a simplified model wherein the point jig was assumed to be a solid line, resolved shear stresses due to the gravitational stress were calculated for the 300-mm-dia wafer, which is considered to be the wafer size of the next generation. On the basis of the previously proposed thermoelastic model, critical stress curves to multiply slip dislocations were obtained as a function of microdefect density, which acts as nucleation sites for dislocation multiplication, thereby softening Si wafers under mechanical stress. By comparing both the gravitational stress and the critical stresses, conditions to suppress slip bands due to the gravitational stress in device processings are described as predictable in wafers larger than 300 mm in diameter and moreover those to suppress slip dislocations due to thermal stress were also predicted. The physical meaning of the critical stress curve is discussed by comparing with the upper yield stress obtained in conventional tensile tests.

Nanoscale characterization of semiconductor materials and devices using scanning probe techniques

Abstract Scanning probe techniques are applied to a rapidly growing degree in the characterization of advanced semiconductor materials and device structures. In this review, the fundamental principles of scanning tunneling microscopy, atomic force microscopy, and other scanning probe techniques are described. The application of these techniques to the characterization of III–V and Group IV semiconductor epitaxial growth and epitaxial layer structure is discussed, with particular emphasis on the elucidation of epitaxial growth mechanisms, and on the atomic-scale characterization of interface and alloy layer structure in III–V heterostructures by crosssectional techniques. Nanoscale characterization of buried metal-semiconductor and semiconductor-semiconductor interfaces using ballistic electron emission microscopy is also addressed. Finally, a detailed discussion is included concerning the use of scanning probe techniques for nanometer-scale characterization of ultrasubmicron Si electronic devices — a problem of central importance in ultralarge-scale integrated circuit technology for the coming decade and beyond. Throughout the review, emphasis is placed on the role of scanning probe microscopy in relation to other semiconductor characterization techniques, the influence of various atomic- to nanometer-scale material properties on semiconductor device behavior, and the importance in many instances of theoretical modeling and simulation in the interpretation of results obtained using scanning probe techniques.

Downscaling ULSIs by using nanoscale engineering

Growing evidence suggests that the fundamental limits of the MOSFET are well below 0.1 μm. However, solving problems involved in building Ultra-Large-Scale Integrated circuits (ULSIs) from MOSFETs with ultimate sizes below the cutting-edge at 0.25 μm will become an increasingly uphill effort. Further downscaling of the ULSI is a great challenge both technologically and economically. Breakthroughs are badly needed, especially in patterning technology. The ULSI has so far been repeatedly refuelled by the right innovation at the right time. There is a strong possibility that the next breakthrough will come from what is now referred to as nanotechnology.

Properties of Fluorinated Silicon Oxide Films Formed Using Fluorotriethoxysilane for Interlayer Dielectrics in Multilevel Interconnections

Properties of a fluorinated silicon oxide (SiOF) film for interlayer dielectrics in multilevel interconnections of ultralarge‐scale integrated circuits (ULSIs) are investigated. The SiOF films are formed by a room temperature chemical vapor deposition (RTCVD) technique using fluorotriethoxysilane [, FTES] and pure water as gas sources. The SiOF film property changes by annealing at 400 or 900°C are studied. Although the Si‒O bond absorption peak position in the Fourier transform infrared (FTIR) spectrum is not changed by 400°C annealing, the peak position for the 900°C annealed SiOF films shifts to low wave numbers. The full width at half‐maximum (FWHM) of the Si‒O bond absorption peak increases by 400°C annealing, and it further increases by 900°C annealing. The tendency of the Si‒F bond peak absorption coefficient change is inverse to the change of FWHM, indicating that fluorine influences the Si‒O bond nature. Other properties such as the fluorine atomic concentration, refractive index, etching rate, shrinkage, residual stress, and leakage current density are changed by the annealing. These property changes are due to changes in the chemical bonding structure. No crack is observed for the SiOF films formed on aluminum wiring patterns after 400°C annealing.

Effect of Fluorine Addition to Plasma-Enhanced Chemical Vapor Deposition Silicon Oxide Film

AbstractOne solution to reduce the time constant of ultra large scale integrated circuit (ULSI) is the use of a low dielectric constant intermetal film like fluorinated silicon oxide (SiOF). We could obtain SiOF films with low dielectric constant as low as 2.6 and good step coverage by adding CF4 to SiH4 and N2O in plasma-enhanced chemical vapor deposition (PECVD) process. To investigate the dielectric constants due to each polarization and the reason for the decrease in the dielectric constant, we used capacitance-voltage (C-V) and ellipsometry measurements, and Kramers-Kronig transformation. The decrease in dielectric constant could not be completely explained by the reduction in ionic and electronic polarization. We could detect silanol groups, Si-OH in the films and their decrease with increasing CF4 flow rate. It is suggested that the main polarization component to decrease dielectric constant is such as orientational polarization. The step coverage of film was improved by adding CF4. It is suggested that the reduction in the sticking probability of films forming species due to the change in surface state improved the step coverage.

Plasma Assisted Chemical Vapor Deposition of Aluminum For Metallization In Ulsi

AbstractAn aluminum thin film for ultra large scale integrated circuits(ULSI) metalization has been formed by PACVD using DMEAA(Dimethylethylamine alane) as a precursor. The selectivity was lost but the conformal step coverage was still maintained when the hydrogen plasma was added to conventional CVD process so that perfectly planarized metalization could be obtained.Comparing to thermal CVD, the reflectivity as well as the resistivity could be much improved especially when the film was deposited on SiO2. The deposition rate and the resistivity of PACVD Al thin films deposited on various substrates such as Si, TiN and SiO2 were compared with those of thermal CVD Al thin films.

Charging effects in plasma immersion ion implantation for microelectronics

The charging effects of plasma immersion ion implantation (PIII) doping experiments have been investigated using a dynamic sheath model and PDP1 plasma simulation code. When the target has a dielectric film, charge accumulation during PIII can have a profound impact on doping results. Under certain process conditions, it can significantly reduce implant energy and dose and thereby alter the implant profile. In addition, it may degrade device reliability, especially for ultralarge-scale integrated circuit devices. In order to minimize charging effects, shorter pulse widths along with moderate values of plasma density and pulse potential should be used.

Fluorinated amorphous carbon thin films grown by plasma enhanced chemical vapor deposition for low dielectric constant interlayer dielectrics

Fluorinated amorphous carbon films were proposed as low dielectric constant interlayer dielectrics for ultralarge scale integration circuits. The films were deposited by plasma enhanced chemical vapor deposition with CH4 and CF4 in a parallel plate rf (13.56 MHz) reactor. The dielectric constant of the amorphous carbon films deposited with CH4 was increased with increases in rf power. The addition of CF4 to CH4 raised the deposition rate and reduced the dielectric constant. At an rf power of 200 W, and at a flow rate of 47 sccm for CF4 and 3 sccm for CH4, the dielectric constant of the fluorinated amorphous carbon films was 2.1.

Fluorinated interlayer dielectric films in ULSI multilevel interconnections

Fluorinated interlayer dielectric films for ultra large scale integrated circuit (ULSI) multilevel interconnections are investigated. The interlayer dielectric film properties and their formation techniques have to meet three requirements such as: (1) a high planarization capability, (2) a low dielectric constant and (3) a low deposition temperature. To satisfy the three requirements, the technologies such as (i) a fluorinated spin-on-glass (SOG) film by fluorotrialkoxysilane vapor treatment (FAST-SOG), (ii) a fluorinated SiO 2 (SiOF) film by room temperature chemical vapor deposition (RTCVD-SiOF) using fluorotrialkoxysilane (FTAS) and pure water as gas sources, (iii) a room temperature liquid phase deposition (LPD) SiO 2 film, and (iv) fluorinated polyimide siloxane (F-PSI) films are desirable. The RTCVD, FAST and LPD techniques have shown the possibility to reduce the film formation temperature to room temperature by catalytic reactions. The dielectric constant for SiO 2 films can be reduced to 3.7 at 1 MHz by using the RTCVD and LPD techniques. The dielectric constant of 2.7 at 1 MHz can be achieved for the F-PSI films, and is lower than those for conventional polyimide films (3.2–3.5) and SiO 2 films (3.9–4.2). Although the FAST-SOG, RTCVD-SiOF and F-PSI films cannot achieve full planarization, the LPD technique can achieve both global and local planarization because this technique has high capability for selective SiO 2 film deposition. The fluorinated films have other good properties such as low residual stress, low residual OH contents and low moisture absorption, which can enlarge the fabrication margins of multilevel interconnections. These other properties are also very effective for improving the ULSI devices performance.

Hydrogen Etching Effects During Plasma Doping Processes and Impact on Shallow Junction Formation

AbstractHydrogen etching effects in plasma ion implantation (PII) doping processes alter device structure and implant dopant profile and reduce the retained implant dose. This has particular relevance to the shallow junction devices of ultra large scale integrated circuits (ULSI). Hydrogen etching of semiconductor materials including Si, poly-Si, SiO2, Al, and photoresist films have been investigated. The effects of varying different PII process parameters are presented. The experimental data show that the spontaneous etching by hydrogen radicals enhanced by ion bombardment is responsible for the etching phenomena. A computer simulation is used to predict the as-implanted impurity profile and the retained implant dose for a shallow junction doping when the etching effect is considered.

Properties of liquid-phase-deposited SiO 2 films for interlayer dielectrics in ultralarge-scale integrated circuit multilevel interconnections

Properties of a new fluorinated SiO 2 film for interlayer dielectrics in multilevel interconnections of ultralarge-scale integrated circuits (ULSIs) are investigated. The fluorinated SiO 2 films are formed at 35 °C by a liquid phase deposition (LPD) technique using a supersaturated hydrofluosilicic acid (H 2SiF 6) aqueous solution. The LPD SiO 2 film surface profiles on polysilicon and aluminum wirings are flat enough, indicating that the LPD technique has good capability for the surface planarization of interlayer dielectric films. The compositions of as-deposited LPD SiO 2 films and those annealed at 400 and 900 °C are SiO 1.85F 0.15, SiO 1.85F 0.15 and SiO 1.90F 0.10 respectively. The LPD SiO 2 film deposition mechanism is explained as follows: (i) fluorosilanols [F n Si(OH) 4− n ] formation; (ii) fluorosilanol oligomer formation by a catalytic reaction in the solution; (iii) oligomer adsorption onto the substrate surface; (iv) oligomer polymerization by a catalytic reaction. The absorption peak position, full width at half-maximum (FWHM) and absorption coefficient for the Si-O bond in the Fourier transform infrared spectra for the as-deposited LPD SiO 2 films are 9.17 micrometer, 0.83 micrometer and 1.19 × 10 6 m -1, respectively, indicating that the films are formed by tightly bonded Si-O networks. The as-deposited LPD SiO 2 films have a refractive index of 1.433, a density of 2.19 × 10 3 kg m -3, an etching rate (measured using 1:30 buffered hydrofluoric acid (HF) solution) of 83 nm min -1, and a residual stress of 20 MPa (tensile). The film shrinkages after annealing at 400 and 900 °C are 0.8% and 2.0% respectively. Although these properties are changed by annealing at 400 and 900 °C, these values are still better than those of SiO 2 films deposited by chemical vapor deposition (CVD) at 400 °C for use as interlayer dielectric films. The LPD SiO 2 films have better electrical properties, such as lower leakage current, higher dielectric breakdown strength (> 6.3 × 10 8 V m -1) and lower dielectric constant (< 3.9 at 1 MHz), than the CVD SiO 2 films.

Electroless Copper Deposition on Metals and Metal Silicides

Chemical plating techniques have been used in silicon processing for many years for junction delineation and ohmic contact formation. In recent years, interest in this area has been renewed because of the potential use of electroless copper deposition for ultra-large-scale integration (ULSI) metallization and for the formation of thin metal etch masks for deep-ultraviolet lithography. Good deposition selectivity, low operating temperature, high copper purity, good filling characteristics, and planar topography have been among the many advantageous attributes reported from early investigations.In the June 1993 issue of theMRS Bulletinon Copper Metallization, Cho et al. gave an exposition on the use of electroless copper for VLSI. More comprehensive reviews of the electrochemical fundamentals can be found in References 8,9, and 10. This article summarizes the current understanding of various chemical and material aspects of this deposition method in an attempt to give an overview of the film growth characteristics for thin film applications. Because of length limitations, only selected topics are included. The emphasis is on the initiation conditions and the resultant microstructure and properties obtained. We also discuss special considerations for fine pattern formation.The information presented here applies primarily to electroless copper deposition on metals and metal silicides since these are the typical substrate surfaces for metallization in contact vias of ULSI circuits. Strictly speaking, metallization of upper-level interconnects occurs mostly on a dielectric base. However, since copper systems usually require a diffusion barrier to shield the copper from diffusing into the silicon, we can treat the deposition process startingfrom this layer onward.