Ultra-deep Submicron Research Articles

Delay analysis of UDSM CMOS VLSI circuits

Propagation delay is one of the important issues for designing and synthesizing any VLSI circuits. In this paper, a simple and accurate delay model has been developed for Ultra Deep Sub-Micron (UDSM) CMOS inverter based on nth power law of MOSFET model when the channel length is in the order of less than or equal to 90nm. Modified model is also applied in the CMOS NANAD2 and CMOS NOR2 in the UDSM range. All the parameters are extracted from BSIM.4.6.1 MOSFET user manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects such as Body Bias effect, Channel Length Modulation effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), etc which may be occurred in the UDSM MOS devices. Our result is better than nth power law and simulation results with respect to propagation delay time. Our proposed model gives an average error of 3.78% & 6.9% with compare to Cadence & Tanner Simulation results respectively.

Bus-Invert 로직변환을 이용한 새로운 저전력 버스 인코딩 기법

UDSM(Ultra Deep SubMicron)기술을 이용한 시스템 온-칩 설계 시 가창 중요한 설계 요소는 버스 상에서의 전력소모와 지연시간을 최소화 하는 것이다. 인접한 선에서 발생되는 crosstalk는 전파 지연을 발생시키는데 지대한 영향을 미치며, 이를 제거하거나 최소화 시키는 일은 SoC(System on a Chip) 설계에서 시스템의 신뢰성 및 성능 향상과 직결된다. 기존의 방법들은 주로 crosstalk 지연이나 버스 스위칭 횟수 중 하나 만을 최소화하는 방법이 제안되었다. 본 논문에서는 인코딩 적용 4 비트 클러스터 상의 버스 스위칭 횟수에 따라 crosstalk과 스위칭 횟수를 동시에 최소화 할 수 있도록 "invert" 기능과 "logic-convert" 기능을 적응적으로 선택하는 새로운 인코딩 기법을 제안한다. 실험결과 제안한 버스 인코딩 기법은 완벽하게 crosstalk 지연를 제거한 반면, 기존의 다른 방법들에 비해 25% 이상 전력을 절약하였음을 보여준다. In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms

Integration of hundreds of processors on a chip will become practical thanks to ultra-deep submicron VLSI technology. As wiring delay becomes a bottleneck for a scalable design, on-chip interconnects turn into the critical issues for system performance and reliability. To mitigate long wiring delay impact, wireless on-chip communication infrastructures featuring hybrid mechanisms exploiting both wired and wireless communications have been proposed. By shortening long distance transmission latency and lowering wired network overhead, overall system transfer latency and energy dissipation are improved accordingly. However, unbalanced traffic management reduces the benefit of high speed wireless links so that wired networks also degrade accordingly. To extract the best performance for these hybrid networks, an intelligent congestion-aware router design is needed to balance traffic load and eliminate congestion delay. A sophisticated routing scheme accommodating more throughput and featuring light weight congestion-aware mechanism which uses the number of blocking buffers as a guideline to avoid serious congestion was designed and evaluated. Modified 7-port routers achieve better performance and the proposed routing algorithm successfully eliminates congestion scenarios and efficiently balances traffic loads. This is the first work to exchange congestion information locally and globally to improve network utilization and transmission quality. The experimental results showed significant improvement in transfer latency, network throughput and power efficiency with moderate hardware cost overhead.

A novel double-trench LVTSCR used in the ESD protection of a RFIC

A low-voltage triggering silicon-controlled rectifier (LVTSCR), for its high efficiency and low parasitic parameters, has many advantages in ESD protection, especially in ultra-deep sub-micron (UDSM) IC and high frequency applications. In this paper, the impact factors of the snapback characteristics of a LVTSCR and the configuring modes are analyzed and evaluated in detail. These parameters include anode series resistance, gate voltage, structure and size of devices. In addition, a double-trench LVTSCR is presented that can increase the hold-on voltage effectively and offers easy adjustment. Also, its snapback characteristics can obey the ESD design window rule very well. The strategy of ESD protection in a RFIC using a LVTSCR is discussed at the end of the paper.

Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications

Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications

Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications

To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS in ultralow power applications. The simulation results show that leakage contributing currents like the subthreshold current, punchthrough current and tunneling leakage current are reduced. The oxide thickness can be increased without increase in the gate induced drain leakage current, and ON-OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is reduced drastically, as well as be applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this work .

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation

In ultra-deep submicrometer technology, soft errors and device aging are two of the paramount reliability concerns. Although many studies have been done to tackle the two challenges, most take them separately so far, thereby failing to reach better performance-cost tradeoffs. To support a more efficient design tradeoff, we propose a unified fault detection scheme—stability violation-based fault detection (SVFD), by which the soft errors (both single event upset and single event transient), aging delay, and delay faults can be uniformly dealt with. SVFD grounds on a new fault model, stability violation, derived from analysis of signal behavior. SVFD has been validated by conducting a set of intensive Hspice simulations targeting the next-generation 32-nm CMOS technology. An application of SVFD to a floating-point unit (FPU) is also evaluated. Experimental results show that SVFD has more versatile fault detection capability for fault detection than several schemes recently proposed at comparable overhead in terms of area, power, and performance.

Characterization analysis of UDSM LVTSCR under TLP stress

The characteristics of a low-voltage triggering silicon-controlled rectifier (LVTSCR) under a transmission line pulse (TLP) and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge (ESD) design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron (UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.

Three-dimensional simulation of total dose effects on ultra-deep submicron devices

The radiation-induced charge distribution in shallow-trench isolation (STI) structures is analyzed in this paper. We present a new approach for modeling total dose effect of ultra-deep submicron transistors. The results show that, when there is no radiation-induced charge in top100 nm of the trench-silicon interface, the simulation results of 0.18μm ultra-deep submicron transistors show that the I-V sub-threshold does not produce the hump, and yield good agreement with experiments. On the aspect of the improvement on total ionizing dose, the leakage current of MOSFET with delta doping can be effectively reduced than with the uniform doping profile under lower radiation dose. If the Halo doping is adopted in landscape orientation, the total dose of ultra-deep submicron transistors can be improved. This improvement is evident even at higher irradiation dose.

Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications

In ultra-deep submicrometer (UDSM) technologies, the current paradigm of using copper (Cu) interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck. In this paper, we perform a system level evaluation of Carbon Nanotube (CNT) interconnect alternatives that may replace conventional Cu interconnects. Our analysis explores the impact of using CNT global interconnects on the performance and energy consumption of several multi-core chip multiprocessor (CMP) applications. Results from our analysis indicate that with improvements in fabrication technology, CNT-based global interconnects can significantly outperform Cu-based global interconnects.

2D and 3D CMOS MAPS with high performance pixel-level signal processing

Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130 nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130 nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.

Effect of Channel Length and Width on NBTI in Ultra Deep Sub-Micron PMOSFETs

The effects of channel length and width on the degradation of negative bias temperature instability (NBTI) are studied. With the channel length decreasing, the NBTI degradation increases. As the channel edges have more damage and latent damage for the process reasons, the device can be divided into three parts: the gate and source overlap region, the middle channel region, and the gate and drain overlap region. When the NBTI stress is applied, the non-uniform distribution of the generated defects in the three parts will be generated due to the inhomogeneous degradation. With the decreasing channel length, the channel edge regions will take up a larger ratio to the middle channel region and the degradation of NBTI is enhanced. The channel width also plays an important role in the degradation of NBTI. There is an inflection point during the decreasing channel width. There are two particular factors: the lower vertical electric field effect for the thicker gate oxide thickness of the shallow trench isolation (STI) edge and the STI mechanical stress effecting on the NBTI degradation. The former reduces and the latter intensifies the degradation. Under the mutual compromise of the both factors, when the effect of the STI mechanical stress starts to prevail over the lower vertical electric field effect with the channel width decreasing, the inflection point comes into being.

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cnt</sub> ) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLL <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cnt</sub> signal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in with major improvements in measurement results and analysis.

Current Estimation Techniques for Reliability Analysis of Semiconductor Interconnects

As process technology for semiconductor goes beyond the ultra-deep submicrometer regime, interconnect reliability on a chip has become a serious design concern. As process parameters scale, interconnect widths are reduced rapidly while the current flowing through the interconnect does not decrease in a proportional manner. This trend increases current densities in metal interconnects which may lead to poor reliability for electromigration. Hence, it is critical to estimate the current amount passing through the interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast yet accurate current estimation technique that can offer not only analysis time equivalent to those offered by the previous approximation methods but also a relatively precise estimation by using closed-form equations. The accuracy of the proposed technique was confirmed to be about 8 times better on average when compared to the previous work.

LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC

As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16-bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR), energy per instruction (EPI), Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.

W-plug via electromigration in CMOS process

We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55 μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3 × 107 s, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.

Status and perspectives of deep N-well 130 nm CMOS MAPS

Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices are fabricated in a commercial 130 nm CMOS process, and the triple well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. Because of the high integration density of such a technology, complex digital functions can be included in each pixel, implementing a sparsified readout architecture of the pixel matrix with time stamping.This paper reviews the features of the ``ILC class'' and ``SuperB class'' MAPS devices, discussing their different design in terms of pixel pitch, analog signal processing, and digital readout architecture. For SuperB, a data-driven, continuously operating readout scheme was adopted along with a macropixel matrix arrangement, whereas for the ILC the matrix is read out in the long intertrain period. In both versions, the address of hit pixels is transmitted off-chip along with the time stamp. The experimental performance of the chips provides an assessment of the Deep N-Well MAPS potential in view of future applications.The paper also discusses the way forward in the development of these devices, outlining the issues that have to be tackled to design full size Deep N-Well MAPS for actual experiments. These sensors could take advantage from technological advances in microelectronic industry, such as vertical integration. The impact of these new technologies on the design and performance of DNW pixel sensors could be large, with potential benefit for various device features, from the charge collection properties to the digital readout architecture.

Multiple Bit Upsets and Error Mitigation in Ultra-Deep Submicron SRAMS

Recent measurements of the SEU (single-event upset) cross-section for 6 T SRAMs fabricated in a nano-scale commercial CMOS process were performed. Results indicated that the dominant upset mechanism was associated with multiple-cell upsets (MCUs) strikes on PMOS transistors. The dominance of the MCU cross section favors the use of a block architecture with widely spaced word bits and the use of EDAC (error detect and correct) along with periodic memory scrubbing to prevent the integration of single-bit errors.

CMOS technologies in the 100 nm range for rad-hard front-end electronics in future collider experiments

130 nm and 90 nm CMOS processes are going to be used in the design of mixed-signal integrated circuits for the readout of detectors in the future generation of HEP experiments. In applications such as inner SLHC detectors, these ultra-deep submicron systems will have to stand total doses of ionizing radiation of the order of 100 Mrad and beyond. While the scaling of the gate oxide thickness to about 2 nm gives a high degree of radiation tolerance, issues such as the gate tunneling current and the sidewall leakage associated to lateral isolation oxides must be investigated. This paper provides an analysis of an extensive set of irradiation tests carried out on 130 and 90 nm CMOS transistors belonging to commercial technologies. With special focus on the design of analog front-end circuits for silicon pixel and strip detectors, the impact of ionizing radiation on the noise performance is evaluated and the underlying physical degradation mechanisms are pointed out to provide criteria for improving radiation hardness properties.

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.