Type Of Non-volatile Memory Research Articles

IPL-P

A great deal of research has been done on solid-state storage media such as flash memory and non-volatile memory in the past few years. While NAND-type flash memory is now considered a top alternative to magnetic disk drives, different types of non-volatile memory have also begun to appear in the market recently. Although some advocates of storage class memory (SCM) predicted that flash memory would give way to SCM in the very near future, we believe that they will co-exist, complementing each other, for a while until the hurdles in its manufacturing process are lifted and storage class memory becomes commercially competitive in both capacity and price. This demo presents an improved design of In-Page Logging (IPL) by augmenting it with Phase Change RAM (PCRAM) in its log area. IPL is a buffer and storage management strategy that has been proposed for flash memory database systems. Due to the byte-addressability of PCRAM and its faster speed for small reads and writes, the IPL scheme with PCRAM can improve the performance of flash memory database systems even further by storing frequent log records in PCRAM instead of flash memory. We report a few advantages of this new design that will make IPL more suitable for flash memory database systems.

(Invited) Nonvolatile Memories for Nano and Giga Electronics

Memory devices are critical elements in ULSIC. It is also desirable to include memory functions in a-Si:H TFTs for new and novel applications. In this paper, the author reviews and discusses recent developments on two types of nonvolatile memories in his laboratory, i.e., the nanocrystals embedded high-k MOS capacitor and the floating-gate a-Si:H TFT. For the former, the structure, device performance, and reliability are examined. For the latter, charge trapping and detrapping mechanisms and memory functions are investigated. Challenges of these devices toward nano and giga electronics are analyzed.

Enhanced Data Retention Characteristic on SOHOS-Type Nonvolatile Flash Memory with CF4-Plasma-Induced Deep Electron Trap Level

The improved data retention characteristics of Polysilicon-oxide-hafnium oxide-oxide-silicon (SOHOS) type nonvolatile memory were obtained by post-HfOB2B trapping layer deposition tetrafluoromethane (CFB4B) plasma treatment. The memory characteristics such as program/erase speed, retention and endurance were studied comprehensively. That fluorine atoms incorporated into Hf-based high-k material eliminate shallow trap defect level effectively and remain deeper trap level. Although the shallow traps of the HfOF trapping layer SOHOS memory have passivated, it doesn't deteriorate the program/erase speed obviously and retention characteristic was then improved because of deeper electron storage level. The results clearly indicate CFB4B plasma treatment-induced deep electron storage level is a feasible technology for future SOHOS-type nonvolatile flash memory application.

Charge-based nonvolatile memory: Near the end of the roadmap?

The floating gate cell has been the workhorse for nonvolatile memories for over 40 years now. Indeed, the original concept as proposed by Kahng and Sze in 1967 [1] has survived the subsequent generations of nonvolatile memory types going from EPROMs and One-Time-Programmable (OTP) memories to EEPROMs and finally ending with the major success technology based on the same concept: Flash memory. The success of Flash has recently made it into the technology driver for the entire silicon industry, not in the least in the area of lithography. However, with this major success, final scaling limitations come into sight at an increasingly more rapid pace and several red brick walls have been identified on the not-so-far horizon. This paper will elaborate on these limitations and challenges and will also propose solutions or onsets of solutions to allow for further conceptual improvement in the area of these charge-based memories with long-term data retention.

Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application

In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bottom layer. A large memory window and long retention time were obtained. However, the thermal electron excitation is dominant for the electron discharge process during retention. How to reduce the defects in MND layer is important for further improving of memory characteristics.

Fault model and test procedure for phase change memory

Chalcogenide-based phase change memory (PCM) is a type of non-volatile memory that will most likely replace the currently widespread flash memory. Current research on PCM targets the integration feasibility, as well as the reliability of such memory technology into the currently used complementary metal oxide semiconductor (CMOS) process. Such studies identified special failure modes, known as disturbs, as well as other PCM specific faults. In this study, the authors identify these failures, analyse their behaviours and develop fault primitives/models that describe these faults accurately and effectively. In addition, the authors propose an efficient test algorithm, called March-PCM, to test for these faults and compare its performance to some previously developed test algorithms.

Progress of High-k Dielectrics Applicable to SONOS-Type Nonvolatile Semiconductor Memories

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

The investigation of an amorphous SiOx system for charge storage applications in nonvolatile memory at low temperature process

Abstract Beside silicon nitride, silicon rich SiO x is a good charge storage material for the charge trap type of nonvolatile memory due to the high density of the charge traps. In this study, the charge storage ability of various amorphous SiO x materials has been investigated. By controlling the ratio of N 2 O/SiH 4 gases from a 1:6 to a 2:1 input gas flow rate, the deposited SiO x bandgap changed from 2.3 to 3.9 eV. The charge storage properties of the SiO x system were studied on metal–insulator–semiconductor structures with an insulator stack of SiO 2 /SiO x /SiO x N y on an n-type silicon wafer. In this structure, the SiO 2 was used for the blocking layer and the SiO x N y was used for the tunneling layer. By analyzing the FTIR and the photoluminescence spectra, it is shown that the richest silicon material incorporates numerous non-bridging oxygen hole-center (NBOHC) defect sources and a rich silicon phase in the base material. These defects, as well as the amorphous silicon clusters that exist in the SiO x layer, enhanced the charge storage capacity of the device compared to the oxygen rich SiO x cases. The retention property was optimized by surveying the tunneling thickness of the 2.3, 2.6, 2.9, and 3.2 nm SiO x N y layers.

Chalcogenide materials and their application to Non-Volatile Memories

Chalcogenide materials are chemical compounds consisting of at least one chalcogen ion, i.e. a chemical element in column VI of the periodic table also known as the oxygen family. More precisely the term chalcogenide refers to the sulphides, selenides, and tellurides. Among the various applications of this class of materials, we review here two types of Non-Volatile Memories (NVM): the Phase Change Memories (PCM) which rely on the rapid crystallisation and high electrical contrast between the amorphous and crystalline phases of some of these compounds, and the Current Bridging Random Access Memories (CBRAM) which make use of the ionic conduction of compounds containing metallic ions.

A durable and energy efficient main memory using phase change memory technology

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories -- the Phase Change Memory (PCM) as the main memory for a 3D stacked chip. The main challenges we face are the limited PCM endurance, longer access latencies, and higher dynamic power compared to the conventional DRAM technology. We propose techniques to extend the endurance of the PCM to an average of 13 (for MLC PCM cell) to 22 (for SLC PCM) years. We also study the design choices of implementing PCM to achieve the best tradeoff between energy and performance. Our design reduced the total energy of an already low-power DRAM main memory of the same capacity by 65%, and energy-delay 2 product by 60%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices

While NAND flash memory is used in a variety of end-user devices, it has a few disadvantages, such as asymmetric speed of read and write operations, inability to in-place updates, among others. To overcome these problems, various flash-aware strategies have been suggested in terms of buffer cache, file system, FTL, and others. Also, the recent development of next-generation nonvolatile memory types such as MRAM, FeRAM, and PRAM provide higher commercial value to non-volatile RAM (NVRAM). At today's prices, however, they are not yet cost-effective. In this paper, we suggest the utilization of small-sized, next-generation NVRAM as a write buffer to improve the .overall performance of NAND flash memory-based storage systems. We propose various block-based NVRAM write buffer management policies and evaluate the performance improvement of NAND flash memory-based storage systems under each policy. Also, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed buffer management policies outperform the traditional page-based LRU algorithm and the proposed optimistic FTL outperforms previous log block-based FTL algorithms, such as BAST and FAST.

High-k HfxGdyOz Charge Trapping Layer in Silicon–Oxide–Nitride–Silicon Type Nonvolatile Memory by In situ Radio Frequency Dual-Sputtering Method

In this paper, we propose a novel non-volatile memory (NVM) with a HfxGdyOz trapping layer prepared by RF dual sputtering for the first time. A higher programming/erasing (P/E) speed and a longer data retention time can be obtained owing to improved trapping ability of HfGdO. Furthermore, in situ RF dual sputtering of HfxGdyOz MHHHS (metal/HfO2/HfxGdyOz/HfO2/Si) is a promising technology for future NVM because of its simplicity and its material compatibility in the semiconductor industry.

Radiation Effects on Programmed NROM Cells

NROM type non-volatile memories, having information charge stored in traps in silicon nitride layer, were subjected to different radiation sources in order to ascertain the radiation hardness. Fundamental device parameters, such as threshold voltage shift and current leakages were studied as function of the accumulated dose for gamma (60Co) and Boron ions irradiations to emulate real radiation environments for space and avionics applications. Radiation tolerance of NROM cells was registered with a pronounced degradation for doses exceeding 50 Krad and 1x1010 B/cm2 for gamma and Boron ions irradiations respectively.

High-k Nd2O3 and NdTiO3 Charge Trapping Layers for Nonvolatile Memory Metal- SiO2-High-k-SiO2-Silicon Devices

In this article, we proposed high- and films as the charge trapping layer in metal-oxide-high--oxide-silicon (MOHOS)-type nonvolatile memory devices. X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy were used to study the structural, compositional, and morphological features of these films after annealing at different temperatures. Compared to the film, a MOHOS-type memory device prepared under the film exhibited superior memory characteristics, such as a higher window of in the capacitance-voltage hysteresis loop, a larger flatband voltage shift of , and a lower charge loss rate of 3% at room temperature. The improvement can be explained by the Ti content in the film, which helps to enhance the grain growth and suppress the formation of interfacial and silicate layer at the /oxide interface, and produce a deeper trap energy level in the .

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Operation properties of polysilicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile semiconductor memory (NVM) devices with stacked tunneling and charge trapping layers were investigated in this work. Clear enhancement on operation speed and satisfactory retention of NVM device were achieved by adopting stacked tunneling oxide. Enhancement on programming speed but degradation on erasing operation was observed for device with stacked charge trapping layer. Finally, operating characteristics of devices with stacked tunneling oxide, stacked charge trapping layer, and combining both stacked tunneling oxide and charge trapping layer were compared and discussed.

Reversible switching characteristics of polyfluorene-derivative single layer film for nonvolatile memory devices

This letter reports on reversible switching behavior of metal-insulator-metal type nonvolatile organic memory devices using polyfluorene-derivative (WPF-oxy-F) single layer film. The current-voltage (I-V) characteristics showed that the WPF-oxy-F single layer film has two distinguished resistance states, low resistance state and high resistance state, with four orders of on/off ratio (Ion∕Ioff∼104). From the analysis of I-V curves, area dependent I-V characteristics, and current images obtained by conducting atomic force microscopy we propose that the space charge limited current with filamentary conduction is a potential mechanism for the reversible switching behavior of WPF-Oxy-F memory devices.

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the system-on-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, cost-effective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit- or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism

Memory technology in the future

This article deals with future memory technologies in the next mobile era. First concern is about whether NAND flash memory and DRAM will succeed to evolve beyond 50 nm technologies. Now, technological needs in both memories play a driving engine in pushing further for scaling of a device dimension. Secondly, entirely different types of non-volatile memories can start to penetrate main memory markets as an alternative of NAND flash memory or DRAM in the not-too-distant future. Along with 3-D access transistors, it is widely accepted that 3-D MIM capacitors with ultra high-K dielectrics and noble electrodes will extend silicon technology down to a technology node between 20 to 30 nm. With charge-trap-flash technology, NAND flash memory will extend its technology node down to 20 - 30 nm. Among the candidates for the next generation, PRAM and FRAM begin to burgeon in mass-production. Beyond a 50 nm technology node, scaling of PRAM could be successful by the development of new material and new cell structure. 3-D ferroelectric-capacitor technology is critical for FRAM to enter a 90 nm technology node and beyond.

Integration of lead zirconium titanate thin films for high density ferroelectric random access memory

Interests are being focused on types of nonvolatile memories such as ferroelectric random access memory (FRAM), phase change random access memory, or magnetoresistance random access memory due to their distinct memory properties such as excellent write performance which conventional nonvolatile memories do not possess. Among these types of nonvolatile memories, FRAM whose cell structure and operation are almost identical to dynamic random access memory (DRAM) can ideally realize cell size and speed of DRAM. Thus FRAM is the most appropriate candidate for future universal memory where all memory functions are performed with a single chip solution. Due to the poor ferroelectric properties of downscaled ultrathin lead zirconium titanate (PZT) capacitors as well as technical issues such as hydrogen and plasma related degradation arising from embedding ferroelectric metal-insulator-metal capacitors into conventional complementary metal oxide semiconductor processes, current FRAM still falls far below its ideally attainable cell size and performance. In this paper, based upon PZT capacitor, current mass-productive one pass transistor and one storage capacitor (1T1C), capacitor over bit line (COB) cell technologies are introduced upon which cell size of 0.937μm2 at 250nm minimum feature size technology node has been realized. And then, most recent 1T1C, COB cell technologies are discussed from which cell size of 0.27μm2 at 150nm minimum feature size technology node has been realized, and finally future three dimensional capacitor technologies for the FRAM with cell size of less than 0.08μm2 beyond 100nm minimum feature size technology node are suggested.

Charge decay characteristics of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures and extraction of the nitride trap density distribution

We investigated the charge decay characteristics of a silicon-oxide-nitride-oxide-silicon type nonvolatile memory at elevated temperatures. Based on the amphoteric trap model and the thermal emission model of the trapped charge, we propose an advanced charge decay model which includes the effect of the bottom oxide, and apply it to extraction of the trap density distribution in energy levels of the nitride layer. The samples prepared have nitride films deposited simultaneously and are classified into two groups according to the thickness of the bottom oxide. The trap density distributions extracted from two groups showed good consistency.