Types Of Gates Research Articles

An Evaluation of a New Type of High Efficiency Hybrid Gate Drive Circuit for SiC-MOSFET Suitable for Automotive Power Electronics System Applications

An Evaluation of a New Type of High Efficiency Hybrid Gate Drive Circuit for SiC-MOSFET Suitable for Automotive Power Electronics System Applications

GPR-Based Framework for Statistical Analysis of Gate Delay under NBTI and Process Variation Effects

With the aggressive scaling of feature size, Negative Bias Temperature Instability (NBTI) and Process Variation (PV) have become major issues for circuit reliability and yield. In this paper, we analyze the variation of gate delay by jointly considering NBTI and PV effects. Using Gaussian Process Regression (GPR) learning interface, a Statistical Gate Delay Extraction (SGDE) framework is proposed. Typical types of logic gates are simulated with commercial 28 nm technology for verifying the performance of SGDE in the experiment. Compared to the golden data, the results show that our proposed approach achieves minimal loss of accuracy with significant runtime speed-up.

Evaluation of Friction and Surface Characteristics of Two Types of Self-Ligating Bracket Gate

Introduction: Frictional forces generation during orthodontic treatment with fixed appliances impedes appropriate tooth movement; hence, research is ongoing to explore “frictionless” techniques. This in vitro study compares Damon Q and Pactive self-ligating metallic brackets in terms of friction and surface characteristics of the bracket gates when using CuNiTi archwires during leveling and alignment stage and examines the effects of aging conditions on frictional force generation. Methods: A total of 108 metallic self-ligating brackets (Damon Q and Pactive) were investigated for frictional resistance with round 0.014″ and rectangular 0.014″*0.025″ CuNiTi archwires post exposure to water storage and acidic attack aging conditions. The bracket gate surface characteristics were evaluated using scanning electron microscope (SEM). Results: There was no statistically significant difference (P > 0.05) in friction generation between the two bracket systems when coupled with 0.014″ CuNiTi archwire, but the Pactive brackets yielded significantly higher frictional forces (P < 0.05) when coupled with 0.014″*0.025″ archwire. The SEM findings revealed nonsignificant differences (P > 0.05) between the surface characteristics of the bracket gates. Conclusions: Damon Q brackets generate low frictional forces, suggesting better performance than Pactive brackets during the first phase of orthodontic treatment. A modified scoring system was developed for an objective description of bracket surface characteristics.

Subtraction Gates: Another Way to Learn Long-Term Dependencies in Recurrent Neural Networks.

Recurrent neural networks (RNNs) can remember temporal contextual information over various time steps. The well-known gradient vanishing/explosion problem restricts the ability of RNNs to learn long-term dependencies. The gate mechanism is a well-developed method for learning long-term dependencies in long short-term memory (LSTM) models and their variants. These models usually take the multiplication terms as gates to control the input and output of RNNs during forwarding computation and to ensure a constant error flow during training. In this article, we propose the use of subtraction terms as another type of gates to learn long-term dependencies. Specifically, the multiplication gates are replaced by subtraction gates, and the activations of RNNs input and output are directly controlled by subtracting the subtrahend terms. The error flows remain constant, as the linear identity connection is retained during training. The proposed subtraction gates have more flexible options of internal activation functions than the multiplication gates of LSTM. The experimental results using the proposed Subtraction RNN (SRNN) indicate comparable performances to LSTM and gated recurrent unit in the Embedded Reber Grammar, Penn Tree Bank, and Pixel-by-Pixel MNIST experiments. To achieve these results, the SRNN requires approximate three-quarters of the parameters used by LSTM. We also show that a hybrid model combining multiplication forget gates and subtraction gates could achieve good performance.

All-type optical logic gates using plasmonic coding metamaterials and multi-objective optimization.

In this article, we propose a multiport plasmonic system (MPS) for implementing all-type logic gates based on coding metamaterials and inverse design technology. Compared to traditional plasmonic logic gates, the coding metamaterials based on metal-dielectric-metal (MDM) structures provide powerful programmability for manipulating electromagnetic (EM) waves and have a compact footprint (0.8 µm × 1.1 µm) for integration. To improve the performance of logic gates, the nondominated sorting genetic algorithm version II (NSGA-II) are used to optimize the distributions of coding metamaterials. After the optimization, the simulation results show that all types of logic gates (AND, OR, NOT, NAND, NOR, XNOR, and XOR) can be obtained with an operating wavelength of 1.31 µm. The maximum extinction ratios between logic states "1" and "0" reach 10.15 dB, 57.54 dB, 43.25 dB, 20.76 dB, 10.42 dB, 24.04 dB, and 27.74 dB for the AND, OR, NOT, NAND, NOR, XNOR, and XOR gates, respectively. Moreover, wavelength-tunable logic operations are also demonstrated to work within a wide spectrum. Our proposed plasmonic system not only provides a universal scheme for implementing all-type compact logic gates for optical processing and computing but also demonstrates effective applications of inverse design in nanophotonic devices.

Robust quantum compilation and circuit optimisation via energy minimisation

We explore a method for automatically recompiling a quantum circuit A into a target circuit B, with the goal that both circuits have the same action on a specific input i.e. B∣in⟩=A∣in⟩. This is of particular relevance to hybrid, NISQ-era algorithms for dynamical simulation or eigensolving. The user initially specifies B as a blank template: a layout of parameterised unitary gates configured to the identity. The compilation then proceeds using quantum hardware to perform an isomorphic energy-minimisation task, and an optional gate elimination phase to compress the circuit. If B is insufficient for perfect recompilation then the method will result in an approximate solution. We optimise using imaginary time evolution, and a recent extension of quantum natural gradient for noisy settings. We successfully recompile a 7-qubit circuit involving 186 gates of multiple types into an alternative form with a different topology, far fewer two-qubit gates, and a smaller family of gate types. Moreover we verify that the process is robust, finding that per-gate noise of up to 1% can still yield near-perfect recompilation. We test the scaling of our algorithm on up to 20 qubits, recompiling into circuits with up to 400 parameterized gates, and incorporate a custom adaptive timestep technique. We note that a classical simulation of the process can be useful to optimise circuits for today's prototypes, and more generally the method may enable `blind' compilation i.e. harnessing a device whose response to control parameters is deterministic but unknown.The code and resources used to generate our results are openly available online \cite{githubLink} \cite{mmaGithubLink}. A simple Mathematica demonstration of our algorithm can be found at questlink.qtechtheory.org.

Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates.

We present an array of 225 field-effect transistors (FETs), where each of them has a graphene monolayer channel grown on a 3-layer deposited stack of 22 nm control HfO2/5 nm Ge-HfO2 intermediate layer/8 nm tunnel HfO2/p-Si substrate. The intermediate layer is ferroelectric and acts as a floating gate. All transistors have two top gates, while the p-Si substrate is acting as a back gate. We show that these FETs are acting memtransistors, working as two-input reconfigurable logic gates with memory, the type of the logic gate depending only on the values of the applied gate voltages and the choice of a threshold current.

Neutron-Induced Pulsewidth Distribution of Logic Gates Characterized Using a Pulse Shrinking Chain-Based Test Structure

This work presents measured data showcasing neutron-radiation induced Single Event Transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulse width distributions. The SET pulse width distributions are obtained from a high density, array-based characterization-vehicle, implemented in 65nm planar CMOS and 16nm FinFET processes, featuring a tunable, high resolution pulse-shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro employs standard logic gate-chains in varying lengths, threshold voltages (VTH) and transistor width flavors as the Devices-Under-Test (DUTs). Measured irradiation data for a range of operating voltages from nominal down to near-threshold reveals the relative impact of the chosen design parameters such as VDD, VTH, device width and the logic chain length as well as their interplay, impacting the overall soft-error susceptibility and the sampled pulse width distributions among the different standard gate types.

Requirements for fault-tolerant quantum computation with cavity-QED-based atom-atom gates mediated by a photon with a finite pulse length

We analyze the requirements for fault-tolerant quantum computation with atom-atom gates based on cavity quantum electrodynamics (cQED) mediated by a photon with a finite pulse length. For short photon pulses, the distorted shape of the reflected pulses from the cQED system is a serious error source. We optimize the cQED system parameters to minimize the infidelity due to the shape distortion and the photon losses in a well-balanced manner for the fault-tolerant scheme using probabilistic gates [H. Goto and K. Ichimura, Phys. Rev. A 80, 040303(R) (2009)]. Our optimization greatly relaxes the requirements for fault-tolerant quantum computation in some parameter regions, compared with the conventional optimization method where only the photon loss is minimized without considering the shape distortion [H. Goto and K. Ichimura, Phys. Rev. A 82, 032311 (2010)]. Finally, we show that reducing the cavity length is an effective way to reduce the errors of this type of gate in the case of short photon pulses.

Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters

Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of Gate (ToG), Hardware Complexity (HC) of Circuit.

Hidroituango Intake Gate Closure - Emergency Conditions

This article presents the investigation, analysis, and results of the intake gate closure of two vertical fixed-wheel gates at the hydroelectric project Ituango in Colombia (2400 MW) under free- flow conditions. This atypical operation was considered successful notwithstanding adverse conditions, and therefore, it can be classified as a unique operation in the field of hydraulic gates. In this article, some relevant parameters, such as the hydraulic force of the servomotor during the operation of the gate, were measured before and after the operation and analyzed, and the results were presented. A new chart is proposed for the downpull coefficient based on the collected data, which could be implemented in the closure of gates against the free flow. Considering the abovementioned factors, the authors propose some recommendations and present drawn conclusions contributing to state of the art on design, manufacturing, and operation of this type of hydraulic gates and structures for large and small dams under adverse and extreme conditions.

Constructing a Facile Biocomputing Platform Based on Smart Supramolecular Hydrogel Film Electrodes with Immobilized Enzymes and Gold Nanoclusters.

Herein, fluorescent gold nanoclusters (AuNCs) and horseradish peroxidase (HRP) were simultaneously embedded into self-assembled dipeptide supramolecular films of N-fluorenylmethoxycarbonyl diphenylalanine (Fmoc-FF) on the surface of ITO electrodes (Fmoc-FF/AuNCs/HRP) by using a simple single-step process. In the films, both the fluorescence property of AuNCs and the bioelectrocatalytic property of HRP were well maintained and could be reversibly regulated by pH-sensitive structural changes in the Fmoc-FF hydrogel films. Cu(II)/EDTA in the solution could lead to the aggregation/disaggregation of AuNCs and further quenching/dequenching the fluorescence signal from the films. Meanwhile, the blue complexes formed by Cu(II) and EDTA could produce a UV-vis signal in the solution. In addition, the coordinated Cu(II) in the films enhanced the electrocatalytic capacity toward the reduction of H2O2 and could switch the current signal. A biomolecular logic circuit was built based on the smart film electrode system by using pH, the concentrations of EDTA, Cu(II) and H2O2 as inputs, while the fluorescence intensity (FL), current (I) and UV-vis extinction (E) of the solution as outputs. Various logic devices were fabricated using the uniform platform, consisting of an encoder/decoder, demultiplexer, dual-transfer gate, keypad lock, digital comparator, half adder, and controlled NOT (CNOT) gate. Specifically, an electronic three-value logic gate, gullibility (ANY) gate, was first mimicked in this biocomputing system. This work not only demonstrated the construction of a new type of multivalued logic gate by using a dipeptide micromolecular matrix but also provided a new approach for designing sophisticated biologic functions, establishing smart multianalyte biosensing or fabricating biology information processing through the use of a simple film system.

Efficient designs of reversible sequential circuits

Recently, the synthesis of reversible sequential circuits has attracted researchers’ attention for implementing low-power logic designs. So far, the direct and replacement techniques have been used in the reversible sequential circuits design. The replacement technique leads to high quantum cost. There is the principle to look for efficient reversible circuits composed of Clifford + T gates by optimizing quantum cost, the number of T gates, and particularly the T-depth of the circuit, which depends on the type and layout of the reversible gates used in the function. This paper has proposed an optimized version of direct feedback technique without any flip-flops and is performed on several samples of reversible circuits design, such as counters and shift registers. It has been shown that by partial changes in the direct technique, quantum cost and other cost metrics have been improved. It has also displayed some efficient designs of the reversible parallel-to-serial converter with parity capability and low-cost design of the control unit for a reversible self-controlled serial adder system. The analysis and comparison depict that all new proposed designs have optimized the existing works in terms of performance variables, including quantum cost, number of T gates, and T-depth of the circuit.

Interplay of Various Charge Sources in AlGaN/GaN Epi-Stack Governing HEMT Breakdown

In this work, we have revealed the interplay of various charge sources (surface, polarization, and buffer) and their relative concentrations across the AlGaN/GaN epi-stack governing the electric field distribution and the breakdown mechanism in high electron mobility transistors (HEMTs). The investigations are carried out for Schottky, metal-insulator-semiconductor (MIS), and p-GaN gate stacks while accounting for possible GaN buffer types (Fe-doped and C-doped). A strong correlation between 3-terminal (3T) breakdown voltage, gate design, and relative concentration of various charges was found. % increase in 3T breakdown voltage when physical dimensions were doubled was also found to be strongly correlated with the relative concentration of various charges for both Fe- and C-doped buffer HEMTs. On the other hand, the 2T (source–drain, without gate, and GaN channel below gate) breakdown voltage was independent of all other parameters except buffer properties and physical dimensions. Physical insights are developed to explain the dependence of electric field distribution, carrier injection, and HEMT breakdown on the surface states, polarization charge, and buffer traps, as well as their relative concentrations for both the buffer types and all three gate types. These insights will help to design efficient surface passivation schemes and resolve ambiguities, often observed in experiments, in terms of location of peak electric field (drain side, or gate side or both) as well as OFF-state conduction and breakdown mechanism (gate injection, or punchthrough, or parasitic conduction through buffer or avalanche generation).

Design and testing of a reversible ALU by quantum cells automata electro-spin technology

Arithmetic logic unit (ALU), a core component of a processor, is one of the thrust areas of the current research. Presently, ALU is designed by transistor-based CMOS technique and its individual components are placed in different layers. The current design is affected by the limitations of Moore’s law and design complexity. At present, ‘Quantum cellular automata electro-spin (QCA-ES)’ technology is widely accepted technology as an alternative of ‘CMOS’ to minimize the above discussed problems. In this research paper, the design of a novel multilayer portable, dynamic, fault-tolerant, power-efficient, thermally stable reversible ALU is proposed which is explored through QCA-ES. All the arithmetic and logical components of ALU are separately placed in different layers. Area density, delay, fault tolerance and thermal stability are investigated. A specific type of gate, known as reversible gate (modified 3:3 ‘TSG’ gate), is used in this proposed design with QCA technology to get the optimized design ALU with low occupied area, complexity, delay and power dissipation. Investigation of a fault-free design and saturated amplitude level (of output) change with respect to temperature increment in the proposed device are also discussed in this paper. Not only the thermal stability (up to 6 k temperature) but also an investigation on cell complexity of the 100% fault-free (against multiple cell-omission, cell-displacement, cell-orientation change and extra cell deposition), multilayer nano-device is represented in this work. ‘QCA-Designer’ software is used in this research work to design and develop layout of the proposed components in quantum-field and find out the occupied area, delay and complexity of proposed design. ‘QCA-Pro’ software is used for getting the value of dissipated power.

Experimental and field verifications of radial gates as flow measurement structures

Abstract Radial gates are common structures in irrigation projects. This paper presents some theory-based equations for explicit estimation of the discharge from a radial gate under free and submerged flow conditions using energy and momentum (E-M) principles. The proposed equations were calibrated using extensive experimental data collected from the literature and this study for three types of radial gate under free and submerged flow conditions. The submergence threshold of radial gates is concluded, based on the concepts of hydraulic jump and the intersection of free and submerged head-discharge curves. The results indicated that the error in estimating the discharge increases under transition ( − 2.5 ≤ Sr% ≤ + 2.5), gate lip (1 < y0/w ≤ 2), and high submerged (yt/y0 ≥ 0.95) flow conditions. However, in these flow limit conditions, the discharge error can be considerably decreased by adjusting the tailwater depth to flow depth just after the gate and using the energy equation for the sections before and after the gate. The efficiency of the proposed methods was evaluated based on the data series from field measurements of radial gates in 29 check structures at irrigation canals in the United States and Iran. The results showed that the discharge could be estimated using the proposed equations in field conditions with acceptable accuracy.

MNAzyme probes mediated DNA logic platform for microRNAs logic detection and cancer cell identification

Here, a MNAzyme probes mediated DNA logic platform was developed for microRNAs (miRNAs) logic detection and cancer cells identification. A series of MNAzyme probes containing the cleavage active center were designed. Four types of logic gates were constructed, including YES, AND, XOR and NOR gate. These logic gates used miRNAs that were high expression in cancer cells as logic inputs and used MNAzyme cleavage amplification reaction to output signals. For the construction of intracellular logic gates, MnO2 nanosheets were used as carriers and cofactor providers. When MnO2 nanoprobes entered the cells through endocytosis, the intracellular glutathione degraded the MnO2 nanosheets to release the cofactor Mn2+ and MNAzyme probes. The MNAzyme probes bound to the miRNAs and catalyze the MNAzyme cleavage amplification reaction, producing enhanced fluorescent signal with “true” output. The logic detection of miRNAs was achieved by integrating information from the AND, XOR and NOR logic gates. Moreover, through the construction of intracellular YES and AND logic gates, the cancer cells identification, especially the identification of same type of cancer cells with different phenotypes was achieved. These experimental results showed that this platform held great promise in accurate diagnosis and treatment of cancer.

A new method for reversible circuit synthesis using a Simulated Annealing algorithm and don’t-cares

The synthesis of reversible circuits is a challenge on which many studies have been conducted. Different algorithms attempt to propose a more optimal implementation for each description of a reversible circuit, using reversible gates. In this paper, an algorithm is proposed which, by a heuristic method using a Simulated Annealing algorithm, tries to find a near-optimal circuit to the given truth table. Unlike previous methods, this method does not necessarily require a correct initial circuit to improve it. It can start from a correct circuit or a near-correct circuit or even from an empty circuit, and tries to get a circuit that is better than the initial circuit. It can also achieve different circuits in different runs that are better than the initial circuit. Finally, from the various circuits that this algorithm has produced in different runs, the best is selected as the final circuit. The proposed algorithm also tries to produce a circuit as simple as possible with respect to don’t-care combinations. Also, the current algorithm does not depend on the type of gates. Any library, including arbitrary reversible gates, can be used in this method.

The idea and sense behind various types of logic gates

The idea and sense behind various types of logic gates

All-optical photonic crystal logic gates for optical computing: an extensive review

Internet-based communication has become a major field, with a user base that is expanding day-by-day. The needs have overloaded the available bandwidth, and higher speed has become a mandatory requirement to satisfy the user demands and increased use of the internet. Therefore, there is a need for high-performance computers due to increasing dependence on computing technology. Optics is emerging as the best possible solution over electronics because it is capable of providing parallel data processing with fewer expenses and greater speed of more than 10,000 times faster than electronic computers. The main building block of optical computing is the all-optical logic gates, which are designed using different techniques. Different types of photonic crystal-based all-optical logic gates have been reviewed in detail by discussing the key characteristics and demonstrating the advantages over the previously available technologies (semiconductor optical amplifier and nonlinear waveguide) that are used to build all-optical logic gates.