Two-stage OTA Research Articles

Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency

A CMOS fully differential multipath two-stage operational transconductance amplifier (OTA) with boosted slew rate and power efficiency is proposed in this paper. The new OTA consists of two gain stages. The basic structure of the proposed OTA is the recycling folded cascode (RFC) structure. By using the multipath technique in the first stage of the proposed OTA, it leads to an increase in gain and a decrease in power consumption. In addition, a high-speed current mirror is applied to increase the phase margin. The second stage with a class-AB amplifier is used to increase the transconductance and slew rate of the output. Moreover, the power efficiency of the proposed OTA is boosted compared to the recycling double-folded cascode (RDFC) OTA. This makes the proposed OTA more appropriate for applications that require low power consumption, such as neural amplifiers. Design and simulation of the proposed OTA is done in 0.18 μm standard CMOS technology with a 1 V supply voltage. Post-layout simulation results of the proposed OTA demonstrate that the OTA dissipates 180 nW of power, while showing a 136.7 dB voltage gain, and 127.1 kHz unity gain frequency for a capacitive load of 30 pF. Thus, compared to the RDFC OTA, the proposed OTA provides a 250 % increase in slew rate and a 20 % increase in PSRR and CMRR, while power consumption is reduced by 10 %. The proposed OTA is robust against process, voltage, and temperature (PVT) variations. The recommended OTA achieves a good figure of merit (FOM) over the previous OTAs.

An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs

An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs

A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair

This work presents a two-stage operational transconductance amplifier suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the first stage and the quasi-floating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the amplifier exhibits a 350 kHz gain bandwidth product and a phase margin of 69° while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.

Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio

An approach for the design of two-stage class-AB OTAs with sub- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1{\boldsymbol {\mu }}\text{A}$ </tex-math></inline-formula> current consumption is proposed and demonstrated. The approach employs MOS transistors operating in subthreshold and allows maximum gain-bandwidth product (GBW) to be achieved for a given DC current budget, by setting optimum distribution of DC currents in the two amplifier stages. Following this strategy, a class AB OTA was designed in a standard 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\boldsymbol {\mu }}\text{m}$ </tex-math></inline-formula> CMOS technology supplied from 1.6-V and experimentally tested. Measured GBW was 307 kHz with 980-nA DC current consumption while driving an output capacitance of 40 pF with an average slew rate of 96 V/ms.

Two-stage class-AB OTA with improved specifications

Two-stage class-AB OTA with improved specifications

A Low-Voltage Two-Stage Enhanced Gain Bulk-Driven Floating Gate OTA

This paper presents a two-stage enhanced gain bulk-driven floating gate OTA (EG-BDFG OTA) using flipped voltage follower (FVF). The gain of the OTA is increased with the help of a self-biased summing stage followed by a conventional common-source stage. To ensure the stability of the proposed two-stage OTA, cascode compensation technique is used. The circuit is designed and simulated in Cadence Virtuoso tool using UMC 0.18-[Formula: see text]m CMOS technology library. The simulation results indicate that the proposed design has an improved voltage gain of 59[Formula: see text]dB that is 3.5 times more than that of the single-stage BDFG-FVF OTA. The linearity of the proposed OTA is almost maintained while enhancing the gain by 42[Formula: see text]dB. The circuit delivers [Formula: see text]65[Formula: see text]dB of HD3 and [Formula: see text]56[Formula: see text]dB of THD when a 0.2-Vpp differential input signal of 1-MHz frequency is applied. The circuit is also verified for process variations at different corners with the aid of Monte Carlo and Corner analyses. The layout of the proposed EG-BDFG OTA is also drawn and presented in the paper.

Two-Stage OTA Sizing Optimization Using Bio-Inspired Algorithms

The analog part of a mixed-signal integrated circuit represents a great amount of the circuit sizing effort. It is necessary to size each device separately and, in cases with several variables, the design space becomes quite large. The analog integrated circuit sizing can be modeled as an optimization problem and solved by optimization heuristics. In this work, we compare three bio-inspired heuristics to size a two-stage CMOS Miller operational transconductance amplifier: Particle Swarm Optimization (PSO), Cuckoo Search (CS) and Firefly Algorithm (FA). The goal is to evaluate the applicability of these heuristics for the analog sizing problem and to determine the best configuration of the algorithms parameters for optimizing performance of the generated circuit, mainly power consumption and silicon area. Results show that PSO and CS are more suitable to find optimized solutions, while FA presents less efficient exploration of the design space. Although PSO is faster and generates good solutions, the best overall solution was achieved with CS algorithm.

Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT ${\Delta \Sigma }$ Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given.

Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology

Being able to solve specific issues and meet specific requirements are the goals of designing a two-stage OTA, but how to optimize the trade-offs among its various performances is another key issue. Conventional two-stage folded cascode operational transconductance amplifier (FCOTA) with Miller compensation is the most commonly used circuit structure, but its low current efficiency makes it less advantageous in terms of the trade-off. Thus in this paper, the two-stage recycling folded cascode OTA (RFCOTA) is introduced for lower consumption without degrading other performances and the embedded cascode current buffer (ECCB) compensation is employed which further increases the phase margin compared to Miller compensation without additional power consumption and chip areas. This shows the two-stage RFCOTA has a more comprehensive optimization of various design trade-offs related to power consumption. The Miller compensated two-stage FCOTA and ECCB compensated two-stage RFCOTA are designed and realized in a 0.18 μm CMOS technology and simulation results show that the RFCOTA has the phase margin enhancement of 7° and 8 dB improvement in dc-gain as well as increase slew rate of 2.16 V/us under the condition of halving power consumption compared with conventional FCOTA.

A two-stage CMOS OTA with enhanced transconductance and DC-gain

An ultra-low-power process-insensitive two-stage OTA working in weak inversion region with enhanced transconductance and DC gain is presented in this paper. The proposed two-stage OTA is based on a bulk-driven input stage with rail-to-rail input voltage range, in which the bulk transconductance is enhanced by means of a partial positive-feedback loop. At the same time, a pseudo-cascode frequency compensation technique is applied in this design to improve the phase margin and accordingly, robust the stability of the proposed OTA. In addition, the proposed composite-transistor structure is used to improve output impedance of the two-stage OTA in weak inversion region. As a result, the improvement of DC gain and gain-bandwidth is obtained. Transistor-level simulations and results in UMC 0.18 $$\upmu \hbox {m}$$ CMOS process confirm the theoretical results. Simulated from a 0.5 V supply voltage, the proposed two-stage OTA achieves a 111.5 dB DC gain, a gain-bandwidth product of 9.5 kHz and a phase-margin of $$66^{\circ }$$ while driving a 15 pF load.

A Low Noise Amplifier for Neural Spike Recording Interfaces.

This paper presents a Low Noise Amplifier (LNA) for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.

Low-voltage process-insensitive frequency compensation method for two-stage OTA with enhanced DC gain

A proposed low-voltage pseudo-cascode frequency compensation technique to improve the phase-margin of the two-stage OTA in weak-inversion region is introduced. Furthermore, a enhanced composite-transistor technique to increase the DC gain of the two-stage OTA in weak-inversion region is also presented in this paper. Both the proposed techniques achieve enhanced performance without requiring any additional power dissipation. To compare the performance advantages of the proposed techniques, two two-stage OTAs were designed in a UMC 0.18μm CMOS process. Simulation results show that the DC gain of the two-stage OTA with enhanced composite-transistor is increased by a factor of 17dB, the unity-gain bandwidth of the OTA with the proposed pseudo-cascode compensation technique improved 18%, the phase-margin of the OTA is increased by 33%, and it is maintained over a factor of 300 (from 5 to 1500nA) scaling in its bias current.

A 2.1 μW 80 dB SNR DT ΔΣ modulator for medical implant devices in 65 nm CMOS

This paper presents a simple and robust low-power ΔΣ modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-VT devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 μW, the modulator obtains 0.4 pJ/step FOM. To the authors' knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order ΔΣ modulators.

Active-RC filters using two-stage OTAs with and without feed-forward compensation

In this study, the design of active-RC filters using opamps with and without feed-forward-compensation is considered. Accurate analysis of the passive compensation scheme suggested in literature for lossless and lossy integrators using feed-forward-compensated opamps is carried out. The compensation for the lossy and lossless integrators using negative impedance converter for active filters using two cascaded gms in place of opamps is explored. Novel building blocks for realising the negative capacitance needed for exact compensation are proposed. To study the efficacy of the proposed compensation technique, a two-integrator loop biquad is considered. The PSPICE simulation results of Tow-Thomas biquad are presented to highlight the performance improvement obtained using the proposed compensation techniques.

Correction to “A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC”

In the above titled paper (ibid., vol. 42, no. 3, pp. 496-507, Mar 07), corrections were made to the schematic diagram of the two-stage OTA (Figure 11).

Accurate estimation of high-frequency harmonic distortion in two-stage Miller OTAs

A simple and comprehensive study of the high-frequency harmonic distortion of two-stage Miller-compensated CMOS OTAs used in inverting configuration is presented. An improved extension of a symbolic approach recently proposed by the authors is adopted here. As a result of a better formalisation, inaccuracies incurred by the original formulation can be avoided and closed-form expressions of second- and third-order harmonic distortion factors are derived, whose precision extends well beyond the amplifier's gain-bandwidth product. The correctness of both this approach and the expressions derived was confirmed by comparison with computer simulations at transistor level.

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.