Two-stage Operational Transconductance Amplifier Research Articles

Implementation of OTA in 90nm Technology with Bandgap Reference Application

Operational Transconductance Amplifier (OTA) is the basic building block of Analog circuit with linear input/output characteristics. Because it associates closely linked parameters like noise and settling performance, the current design methodologies for two-stage OTAs frequently result in sub-optimal solutions. The study discusses the implementation of an Operational transconductance amplifier (OTA) with a bandgap reference (BGR) circuit and its importance in providing a stable and accurate reference voltage for various analog and digital circuits. The combination of OTA and BGR provides a stable and accurate reference voltage that can be used in various analog and digital circuits. OTAs are used to drive high capacitive loads. To scale the dimensions of Complementary Metal Oxide Semiconductor (CMOS) technology requires proportional scaling, also taking supply voltage into consideration. In addition to the simplicity and strong performance that the Band Gap Reference (BGR) achieves as a load for the OTA circuit, the architecture of OTA with BGR as load is easily adaptable to attain high accuracy. Because the performance of the used amplifier has a significant impact on the OTA’s performance, consideration must be given to the design and its architecture. Therefore, it is essential to carry out a comparison analysis in order to get the optimal results of the outputs of OTA having BGR as the load.

A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair

This work presents a two-stage operational transconductance amplifier suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the first stage and the quasi-floating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the amplifier exhibits a 350 kHz gain bandwidth product and a phase margin of 69° while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.

A 29.5 dBm OOB IIP3 TIA Based on a Two-Stage Pseudo-Differential OTA With R-C Compensation and Cascode Negative Resistance

This paper presents a highly linear and wideband transimpedance amplifier (TIA) suitable for 5G Sub-6 GHz surface acoustic wave (SAW) filter-less receivers (RX). It is known that for the baseband TIA in a SAW-less RX, the high out-of-band (OOB) linearity is necessary to cope with huge OOB blockers. In other words, the input impedance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z_in</i> ) of the TIAs should be as low as possible, which in turn necessitates high-gain, large-bandwidth (BW) operational transconductance amplifiers (OTA). In this work, a pseudo-differential two-stage OTA with 46 dB open-loop gain and 1 GHz unity-gain loop bandwidth (UGLB) is designed at low supply voltage (Vdd). To stabilize the differential mode (DM) loop, the phase margin (PM) is compensated with the zeros generated by the series of resistors and capacitors (R-C), and the gain margin is improved by the feed-forward technique. To stabilize the common mode (CM) loop without the degradation of the DM gain, a wideband common mode rejection (CMR) technique named cascode negative resistance (CNR) is proposed. This TIA prototype is implemented in a 40 nm low-power (LP) CMOS technology. The measured results show that the TIA achieves 56 MHz BW and 29.5 dBm OOB IIP3. The input impedance is below 29Ω in the concerned frequency range and the in-band (IB) input referred noise (IRN) is 120 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">uV_RMS</i> . The total chip power consumption is around 8.5 mW at 1.2 V supply voltage and the core area is as small as 0.015 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design of Two stage OTA with Optimised Compensation Capacitance

A two-stage operational transconductance amplifier is constructed and compared between 45nm and 180nm CMOS technology in this paper. To find the best design, the suggested operational amplifier is examined across a number of distinct parameters. With a supply voltage of 1.8V, it reaches a maximum gain of about 66 dB and a phase margin of 82°. A Cadence Virtuoso-based circuit simulator has been used to construct the suggested operational amplifier and the comparison is done. Keywords: OTA, Miller coupling capacitance, cadence virtuoso, Gain, output swing, power dissipation.

Tunnel-FET Evolution and Applications for Analog Circuits

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.

A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

This paper presents a new placement and routing method for layout generation of CMOS operational amplifiers (op-amps). Both circuit sizing and layout generation stages are performed automatically. In the proposed method, layout effects are considered during the layout generation. Layout parasitics and geometry information are extracted from a new automated layout generator. In this method, the multi-objective evolutionary algorithm based on decomposition (MOEA/D) is used as an optimization algorithm. In order to verify the performance of the proposed method, the design of three-stage operational amplifier (op-amp) and two-stage class-AB operational trans-conductance amplifier (OTA) in a 0.18µm process CMOS technology with 1.8 V supply voltage are presented. The simulation results indicate the efficiency of the proposed analog layout generation method.

Voltage gain improvement of the operational transconductance amplifier designed with silicon-on-insulator fin field effect transistor after being exposed to proton-irradiation

In this work, the influence of proton-irradiation in the voltage gain of two-stage operational transconductance amplifier (OTA) designed with silicon-on-insulator (SOI) fin field effect transistors (FinFETs) is studied. The OTA simulations were performed using Verilog-A approach based on experimental data extracted from the SOI FinFET electrical characterization, before and after proton-irradiation. The OTA is designed with SOI FinFETs of fin widths (W fin) of 20 nm, 120 nm, and 870 nm, all in the same predefined inversion region (g m/I D = 8 V−1). All evaluated OTA circuits exposed to proton-irradiation presented a voltage gain increase (compared with pre-irradiation circuits), of 0.87 dB, 1.19 dB, and 6.16 dB for fin widths of 20 nm, 120 nm, and 870 nm, respectively. The results show that despite the typical radiation effect of degradation of the individual transistors (it being more severe for larger fin width SOI FinFET), these effects combined in OTA circuits result in an unexpected improvement in DC voltage gain, especially for wider fins. Focusing on the fin width impact on the OTA voltage gain, before and after proton-irradiation, it is much greater for narrow fin width SOI FinFET thanks to the better Early voltage.

Analog design with Line-TFET device experimental data: from device to circuit level

This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog applications. It presents the DC and small signal characteristics of these devices and compares them with other TFET topologies and with conventional MOSFET technology. The Line-TFET’s saturation characteristics are also closely studied, through simulations and experimental characterization, revealing that point tunneling leakage from source to drain not only limits the bias voltage and the gate area but also makes the output conductance independent of the gate length. A common source stage is designed to illustrate and further explore this fact, making comparisons with conventional MOSFET technology. In order to obtain an amplifier with very high voltage gain, a two-stage operational transconductance amplifier is designed considering two different starting points: fixed transistor efficiency (gm/Ids) or fixed normalized current (Ids/W) in order to obtain similar conditions of performance for Line-TFET and MOSFET devices. It is revealed that the Line-TFET design always achieves much higher intrinsic voltage gain (of up to 115 dB) and is more suitable for low power, low frequency applications. Thus, a third design is performed with Line-TFET devices by using gate lengths of 100 nm, achieving 71 dB of open loop voltage gain and 18 nW of power dissipation, which may be suitable for applications such as bio-signal acquisition.

Two-Stage OTA Sizing Optimization Using Bio-Inspired Algorithms

The analog part of a mixed-signal integrated circuit represents a great amount of the circuit sizing effort. It is necessary to size each device separately and, in cases with several variables, the design space becomes quite large. The analog integrated circuit sizing can be modeled as an optimization problem and solved by optimization heuristics. In this work, we compare three bio-inspired heuristics to size a two-stage CMOS Miller operational transconductance amplifier: Particle Swarm Optimization (PSO), Cuckoo Search (CS) and Firefly Algorithm (FA). The goal is to evaluate the applicability of these heuristics for the analog sizing problem and to determine the best configuration of the algorithms parameters for optimizing performance of the generated circuit, mainly power consumption and silicon area. Results show that PSO and CS are more suitable to find optimized solutions, while FA presents less efficient exploration of the design space. Although PSO is faster and generates good solutions, the best overall solution was achieved with CS algorithm.

84 dB DC‐gain two‐stage class‐AB OTA

Operational trans-conductance amplifiers (OTAs) are an essential building block in analogue and mixed-signal circuits. In this study, a new two-stage class-AB OTA is proposed. The class-AB operation is obtained without extra power dissipation, and without unity-gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC-gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state-of-the-art designs.

Design of Two-Stage Fully-Differential Operational Transconductance Amplifier Using a Standard 0.35µm CMOS Process

The paper presents a design of a two-stage fully-differential operational transconductance amplifier (OTA) for a 10-bit 40-Msamples/s Nyquist rate analog-to-digital converter (ADC) using  a standard 0.35µm complementary metal-oxide semiconductor (CMOS) process. A telescopic cascode topology is implemented as main stage, with common source amplifiers as output stage for the differential outputs. The open loop amplifier achieved a gain of 108dB, while the closed loop gain is at 12dB with settling time of less than 11ns for an accuracy of 0.5%. Total output noise achieved is 63.4uVrms. Loop unity gain bandwidth is 205MHz with phase margin of 77.6°. The design has a dynamic range of 88.3dB, and power consumption of 26.6mW from a 3V supply.

98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

In this paper, a new two-stage class-AB operational trans-conductance amplifier (OTA) is proposed. Using active loads in the first stage and improved recycling structure, the effective trans-conductance of the first stage is increased. The nonlinear current mirrors boost the current of the second stage in the slewing mode, leading to the increase of the slew rate (SR). Exploiting the multi-path scheme and increasing the effective trans-conductance cause the OTA DC-gain to be enhanced. The proposed OTA has been fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The OTA exhibits 98 dB DC-gain and 21 MHz unity-gain bandwidth with a 100 pF capacitive load, consuming 3 mW from 1.8 V supply voltage.

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-[Formula: see text]m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2[Formula: see text]dB with a bandwidth between 0.25[Formula: see text]Hz to 28[Formula: see text]kHz, integrated input referred noise of 5.79[Formula: see text][Formula: see text]Vrms and noise efficiency factor of 3.16. The IC consumes 2.4[Formula: see text][Formula: see text]W at 1.2[Formula: see text]V supply and the die area is 0.09[Formula: see text]mm2.

Analysis and Design of Continuous-Time Delta–Sigma Converters Incorporating Chopping

Chopping the operational transconductance amplifier (OTA) of the input integrator in a CT $\Delta \Sigma \text{M}$ is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA- $RC$ integrators that use two-stage feedforward-compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CT $\Delta \Sigma \text{M}$ , which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 $\mu \text{W}$ from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a $1/f$ noise corner of about 3 Hz when chopped at $f_{s}/24$ .

Design and Analysis of Two-Stage Operational Transconductance Amplifier with Compensation Capacitor

Design and Analysis of Two-Stage Operational Transconductance Amplifier with Compensation Capacitor

0.5 V, high gain two-stage operational amplifier with enhanced transconductance

ABSTRACTAn ultra-low-power, bulk-driven (BD) two-stage operational transconductance amplifier (OTA) operating in weak inversion region with enhanced transconductance is introduced. The aim is to boost the transconductance of OTA by using multiple current shunt auxiliary differential amplifiers in positive feedback through source degeneration circuits at input stage. The OTA employs a class AB amplifier at the output stage for high DC gain, while ensuring rail-to-rail operation. The overall OTA is realised in 180 nm complementary metal-oxide semiconductor standard process and its operation is validated through worst-case post-layout simulations at 0.5-V power supply. The OTA drives a maximum bias current of 48 nA achieving an open-loop DC gain of 78 dB, 1.6 μV/√Hz input referred noise at 1 kHz, total harmonic distortion of −66.35 dB and power consumption of 35 nW. The amplifier results in a remarkable improvement in slew rate, unity gain bandwidth and offers a transconductance of at least 10 times to that of conventional BD OTAs.

Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs

This paper presents a fully integrated on-chip switched-capacitor (SC) DC–DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (VL_dw) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (VL_dw). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC–DC converter is designed and simulated using high-voltage 0.35 μm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (IL = 15 mA at VL_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.

Two-stage class-AB OTA with enhanced DC gain and slew rate

ABSTRACTThis article proposes a new two-stage class-AB operational trans-conductance amplifier (OTA). In this OTA, the characteristics of class-AB are applied in both of the stages. By increasing the effective trans-conductance of the first stage, DC gain is improved. Non-linear current mirror boosts the current of the second stage; therefore, slew rate (SR) is increased. In order to verify the performance of the proposed OTA, some simulations are carried out in a 0.18-μm CMOS process in which the supply voltage is 1.8 V. The simulation results indicate 21-dB enhancement in DC gain and 2.7 times improvement in SR compared to its conventional counterpart. The post-layout and Monte Carlo simulations show the proposed OTA has better performance than the state-of-the art designs.

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

SummaryThis paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley &amp; Sons, Ltd.

A 0.6-V, 0.4-µW bulk-driven operational amplifier with rail-to-rail input/output swing

In this paper by using Gm-C compensation technique, an ultra-low-power two-stage operational transconductance amplifier (OTA) with full rail-to-rail input/output swing is presented. The proposed configuration consists of composite transistors, improved bulk-driven folded cascode (FC) structure, feed-forward compensation path and high-speed current mirrors. In comparison with the typical FC, the proposed input stage structure has the benefit of transconductance enhancement with the same power consumption without adversely affecting the noise and offset performance. The presented OTA is simulated in 0.18 μm CMOS technology and the simulation results confirm the theoretical analyses. The proposed amplifier exhibits a DC gain enhancement of 9.5 dB as well as 100 % improvement in gain-bandwidth compared to the conventional FC input stage structure. Finally, the amplifier consumes 400 nW @ 0.6 V supply voltage which makes it suitable for ultra-low-power applications.