Abstract
This paper presents a fully integrated on-chip switched-capacitor (SC) DC–DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (VL_dw) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (VL_dw). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC–DC converter is designed and simulated using high-voltage 0.35 μm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (IL = 15 mA at VL_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.
Highlights
As the popularity of portable smart devices such as smart phones and tablet personal computers (PCs) continues to increase, the extension of battery-life time of smart devices has attracted much attention in recent years
The SC DC–DC converter consists of capacitors and switches, which are driven by two non-overlapping clock signals
In order to effectively visualize the degrees of the efficiency drop, which increase when the converter set to support of four different output load voltage levels
Summary
As the popularity of portable smart devices such as smart phones and tablet personal computers (PCs) continues to increase, the extension of battery-life time of smart devices has attracted much attention in recent years. As voltage drops between the global power supply and the local power supplies increase, the collective power loss from the linear regulators becomes significant. For this reason, developing more power-efficient alternatives that show low peak-to-peak output ripple voltage, with a minimal area cost of achieving higher efficiency in a wide range of the output load voltages, is required.
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