Two-stage Operational Amplifier Research Articles

Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics

Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. In this paper, we advance a novel optimization strategy that explicitly handles the error of the model in the course of optimization. The innovation is in enabling the successive refinement of transistor models within gradually reducing ranges of operating conditions and dimensions. Refining via a brute force requires exponential complexity. The key contribution is the development of a framework that optimizes efficient convex formulations, while using SPICE as a feasibility oracle to identify solutions that are feasible with respect to the accurate behavior rather than the fitted model. Due to the poor posynomial fit, standard GP can return grossly infeasible solutions. Our approach dramatically improves feasibility. We accomplish this by introducing robust modeling of the fitting error's sample distribution information explicitly within the optimization. To address cases of highly stringent constraints, we introduce an automated method for identifying a true feasible solution through minimal relaxation of design targets. We demonstrate the effectiveness of our algorithm on two benchmarks: a two-stage CMOS operational amplifier and a voltage-controlled oscillator designed in TSMC 0.18 μm CMOS technology. Our algorithm is able to identify superior solution points producing uniformly better power and area values under a gain constraint with improvements of up to 50% in power and 10% in area for the amplifier design. Moreover, whereas standard GP methods produced solutions with constraint violations as large as 45%, our method finds feasible solutions.

A low-power low-voltage slew-rate enhancement circuit for two-stage operational amplifiers

A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers. The enhancer utilizes the class-AB input stage to improve current efficiency, while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier. During the slewing period, the enhancer detects input differential voltage of the amplifier, and produces external enhancement currents for the amplifier, driving load capacitors to charge/discharge faster. Simulation results show that, for a large input step, the enhancer reduces settling time by nearly 50%. When the circuit is employed in a sample-and-hold circuit, it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB. The proposed circuit is very suitable to operate under a low voltage (1.2 V or below) with a standby current of 200 μA.

On the design of a low-voltage two-stage OTA using bulk-driven and positive feedback techniques

This article presents the design and simulation of a fully differential two-stage operational transconductance amplifier (OTA) in a 0.18 µm CMOS process with a 0.9 V supply voltage. For this purpose, both the bulk-driven and positive feedback techniques are employed. These techniques increase the DC gain by about 18.5 dB without consuming more power and changing the unity-gain bandwidth and phase margin of the OTA.

Hierarchical sizing and biasing of analog firm intellectual properties

A hierarchical sizing and biasing methodology for analog firm intellectual properties (IPs) is presented. An analog firm IP designates an unsized transistor netlist of an analog circuit. The methodology sizes and biases an analog firm IP by automatically generating suitable sizing procedures. The generated procedures respect topology constraints, designer's hypotheses and design constraints. The procedures are represented using dependency graphs. The methodology deals with different aspects of analog design problems such as MOS inversion level control, insufficient or excess design parameters, systematic offset and negative-feedback. Its application in both fields of analog synthesis and simulation is outlined. The proposed methodology has been successfully used to size, bias and analyze two analog IPs: a single-ended two-stage operational amplifier and a fully differential transconductor. This is performed using 130nm CMOS technology with VDD=1.2V. The results prove the effectiveness and precision of the proposed methodology.

Design Procedures for a Fully Differential Telescopic Cascode Two-Stage CMOS Operational Amplifier

In this paper, a fully differential telescopic operational amplifier design is presented which achieve both high dc gain and high unity-gain frequency. Trade-offs among such factors as bandwidth, gain, phase, margin, bias current, signal swing, slew rate, and power are made evidently. The characteristic of this kind of two-stage operational amplifier is investigated theoretically, in this paper. The results indicate that proposed two-stage operational amplifier achieves broader unity bandwidth, increases the DC gain. Simulation results show that, at 5V power supply, the output swing is ±4.3V, settling time is 167.4ns. Based on the two-stage operational amplifier structure, the operational amplifier with 2.5V output common voltage shows a DC gain greater than 87dB, Gain Bandwidth over 39MHz (5pF load) and a phase margin larger than 84° with power dissipation of 3mW. These good results could be used in Σ-△ modulation and A/D conversion etc.

High-Performance CMOS Current Mirrors: Application to Linear Voltage-to-Current Converter Used for Two-Stage Operational Amplifier

This paper presents two schemes of high performance CMOS current mirror, one of them is used for operational tran-sconductance amplifier (OTA) in analog VLSI systems. The linearity, output impedance, bandwidth and accuracy are the most parameters to determine the performance of the current mirror. Here a comparison of two architectures based on same architecture of the amplifier is presented. This comparison includes: linearity, output impedance, bandwidth and accuracy. These two circuits are validated with simulation in technology AMS 0.35 μm. An operational amplifier based on the adapted current mirror is proposed. Its frequency analysis with large bandwidth is validated with the same technology.

Optimization design of two-stage operational amplifier with frequency compensation via geometric programming

An optimization design technique to obtain global solution for a two-stage operational amplifier (op-amp) with frequency compensation is presented. This frequency compensation technique can adjust the equivalent resistance to guarantee that the phase margin is stable even though circumstance temperature varies. Geometric programming is used to optimize the component values and transistor dimensions. It is used in this analog integrated circuit design to calculate these parameters automatically. This globally optimal amplifier obtains minimum power while other specifications are fulfilled.

Analog layout retargeting using geometric programming

To satisfy the requirements of complex and special analog layout constraints, a new analog layout retargeting method is presented in this article. Our approach uses geometric programming (GP) to achieve new technology design rules, implement device symmetry and matching constraints, and manage parasitics optimization. The GP, a class of nonlinear optimization problem, can be transferred or fitted into a convex optimization problem. Therefore, a global optimum solution can be achieved. Moreover, the GP can address problems with large-scale variables and constraints without setting an initialization variable range. To meet the prerequisites of the GP methodology for analog layout automation, we propose three kinds of mathematical transformations, including negative coefficient transformation, fraction transformation, and maximum of posynomial transformation. The efficiency and effectiveness of the proposed algorithm, as compared with the other existing methods, are demonstrated by a basic case-study example: a two-stage Miller-compensated operational amplifier and a single-ended folded cascode operational amplifier.

Mixed-Signal Organic Integrated Circuits in a Fully Photolithographic Dual Threshold Voltage Technology

Analog & digital circuits implemented in a dual threshold voltage (VT) p-channel organic technology are presented. The dual VT organic technology is compatible with large-area and mechanically flexible substrates due to its low processing temperature (≤ 95°C) and scalable patterning techniques. We demonstrate the first analog & digital organic integrated circuits produced by a dual-gate metal process. The analog circuits are powered by a 5-V supply and include a differential amplifier and a two-stage uncompensated operational amplifier (op-amp). A dynamic comparator is measured to have an input offset voltage of 200 mV and latching time of 119 ms. Both the comparator and the op-amp dissipate 5 nW or less. Area-minimized digital logic is presented. Inverters powered by a 3-V supply were measured to have positive noise margins and consumed picowatts of power. An 11-stage ring oscillator, also powered by a 3-V supply, swings near rail to rail at 1.7 Hz. These results demonstrate dual threshold voltage process feasibility for large-area flexible mixed-signal organic integrated circuits.

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters

This paper presents the design of a two-stage bulk-input pseudo-differential operational transconductance amplifier (OTA) and its application in active-RC filters. The OTA was designed in 90 nm CMOS process and operates at a single supply voltage of 0.5 V. Using a two-path bulk-driven OTA by the combination of two different amplifiers the DC gain and speed of the OTA is increased. Rail-to-rail input is made possible using the transistor’s bulk terminal as in input. Also a Miller-Feed-forward (MFF) compensation is utilized which is improved the gain bandwidth (GBW) and phase margin of the OTA. In addition, a new merged cross-coupled self-cascode pair is used that can provide higher gain. Also, a novel cost-effective bulk-input common-mode feedback (CMFB) circuit has been designed. Simplicity and ability of using this new merged CMFB circuit is superior compared with state-of-the-art CMFBs. The OTA has a 70.2 dB DC gain, a 2.5 MHz GBW and a 70.8o phase margin for a 20 PF capacitive load whereas consumes only 25 µw. Finally, an 8th order Butterworth active Biquadrate RC filter has been designed and this OTA was checked by a typical switched-capacitor (SC) integrator with a 1 MHz clock-frequency.

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13-μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.

A Resistor-Compensation Technique for CMOS Bandgap and Current Reference with Simplified Start-Up Circuit

This paper presents a resistor-compensation technique for a CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in the 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. The measurements verify a current reference of 735.6nA, the voltage reference of 888.1mV, and the power consumption of 91.28µW at a supply voltage of 3.3V. The voltage TC is 49ppm/°C in the temperature range from 0°C to 100°C and 12.8ppm/°C from 30°C to 100°C. The current TC is 119.2ppm/°C at temperatures of 0°C to 100°C. Measurement results also demonstrate a stable voltage reference at high temperature (> 30°C), and a constant current reference at low temperature (< 70°C).

A New Power-Consumption Optimization Technique for Two-Stage Operational Amplifiers

This paper proposes a technique for two-stage operational amplifiers (OPAMPs) to optimize power consumption according to various channel conditions of wireless communication systems. The proposed OPAMP has the ability of reducing the quiescent current of each stage independently by introducing additional common-mode feedback, therefore more optimization is possible according to the channel conditions than conventional two-stage OPAMPs. The simulations verify the benefits of the technique. As a proof-of-concept topology, the proposed OPAMPs were used in a channel-selection filter for a multi-standard mobile-TV receiver. The power consumption of the filter, 3.4-5.0mW, was adjustable according to the bandwidth, the noise, and the jammer level. The performance of the filter meets the requirements and verifies the effectiveness of the proposed approach. The filter was fabricated in 0.18-µm CMOS and occupied 0.64mm2.

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 μm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 μV and the error introduced by the rectification with respect to the non rectified signal is less than ?100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.

Design criterion for high-speed low-power SC circuits

The settling behavior of switched-capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two-stage Miller-compensated operational amplifiers (op-amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op-amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35- µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.

A Novel Low-Power CMOS Operational Amplifier with High Slew Rate and High Common-Mode Rejection Ratio

Problem statement: High speed operational amplifier is always an on-go ing research topic since major high speed application are needed. Approach: A two-stage operational amplifier (op amp) is designed, simulated and fabricated using a UMC 0 .5 µm 2P2M CMOS technology. Results: This chip includes a compensation technique to ensure st ability and zero systematic input-offset-voltage. The fabricated chip achieves a 84 dB open loop gain , a 24 V µS -1 slew rate, a 84 dB CMRR utilizing a capacitive load of 5 pF, a 30 MHz unity gain frequency and consumes 2.8 mW from a 2.5 V power supply. Conclusion: The proposed chip, which is the first available CMO S operational amplifier in Jordan as the authors are aware, is we ll-suited to low-voltage applications since it does not require cascade output stages.

Frequency compensation for two-stage operational amplifiers with improved power supply rejection ratio characteristic

A frequency compensation technique improving characteristic of power supply rejection ratio (PSRR) for two-stage operational amplifiers is presented. This technique is applicable to most known two-stage amplifier configurations. The detailed small-signal analysis of an exemplary amplifier with the proposed compensation and a comparison to its basic version reveal several benefits of the technique which can be effectively exploited in continuous-time filter designs. This comparison shows the possibility of PSRR bandwidth broadening of more than a decade, significant reduction of chip area, the unity-gain bandwidth and power consumption improvement. These benefits are gained at the cost of a non-monotonic phase characteristic of the open-loop differential voltage gain and limitation of a close-loop voltage gain. A prototype-integrated circuit, fabricated based on 0.35 µm complementary metal-oxide semiconductor technology, was used for the technique verification. Two pairs of amplifiers with the classical Miller compensation and a cascoded input stage were measured and compared to their improved counterparts. The measurement data fully confirm the theoretically predicted advantages of the proposed compensation technique.

A four-channel microelectronic system for neural signal regeneration

This paper presents a microelectronic system which is capable of making a signal record and functional electric stimulation of an injured spinal cord. As a requirement of implantable engineering for the regeneration microelectronic system, the system is of low noise, low power, small size and high performance. A front-end circuit and two high performance OPAs (operational amplifiers) have been designed for the system with different functions, and the two OPAs are a low-noise low-power two-stage OPA and a constant-gm RTR input and output OPA. The system has been realized in CSMC 0.5-μm CMOS technology. The test results show that the system satisfies the demands of neuron signal regeneration.

Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization

In this paper, we present application and effectiveness of Particle Swarm Optimization (PSO) for automatic sizing of analog circuits. An efficient re-initialization strategy is introduced to improve the performance of PSO Algorithm (referred as PSO-R). Four benchmark circuits, namely, (i) CMOS buffer chain, (ii) two-stage CMOS operational amplifier (op-amp), (iii) high-gain low-power low-voltage three-stage CMOS op-amp, and (iv) a recently reported ultra-low-power ultra-low-voltage CMOS Miller operational transconductance amplifier (OTA), are automatically designed using the PSO-R algorithm. For the purpose of comparison, these circuits are also designed using PSO, Hierarchical PSO (HPSO), and Genetic Algorithm (GA). Various CMOS technologies ranging from 0.35 μm down to 0.13 μm are used. PVT (process, voltage, and temperature) variations are taken into account and Spectre tool is used for circuit simulations. The PSO-R algorithm converges to a better solution compared to other algorithms for multiple design trials of various low-power low-voltage op-amp designs. For CMOS ultra-low-power ultra-low-voltage Miller OTA, even performance of the circuit designed by the PSO-R algorithm is better than that of recently reported manual design of the same circuit. For future ultra-low-voltage applications, this OTA is also designed in 0.4 V supply voltage. This 0.4 V OTA gives a DC gain of 75 dB, unity gain frequency of 50 MHZ, and dissipates a power of 550 nW. For this design, PSO-R algorithm has taken 19 minutes of CPU time on average on a Sun system with 1.2 GHz dual core processor and 8 GB RAM.

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57dB at 2MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712LSB. The dynamic range of the ADC is 58.72dB for full-scale input signal at 2MHz input frequency. The ADC consumes 52.6mW at 100MS/s sampling rate. The circuit is implemented using UMC-180nm digital CMOS technology.