Turn-on Energy Loss Research Articles

Numerical analysis of an ultralow switching loss IGBT with super junction and blocking junction

In order to reduce the switching loss (ESW) and enhance the breakdown voltage (BV), in this paper, an insulated gate bipolar transistor with an internal blocking junction and super junction (SJBJ-IGBT) is proposed and investigated. By inserting P-pillar and N-pillar on both sides of the drift region, a drift area with auxiliary depletion function can be formed. The junction of the primary blocking layer (JPB) is located internally in the device’s drift region. The JPB is reverse biased and withstand the main E-field during device turn-off. Meanwhile, the JPB is surrounded by P-pillar and N-pillar, reducing the E-field(E-field) peak value of device, and making E-field distribution more uniform. Furthermore, during device turn-on, the reduction of the effective area of drift region makes it easier for the JPB side of the P-drift region to accumulate excess holes. So that the SJBJ-IGBT is easier to turn-on. The snapback phenomenon of SJBJ-IGBT is eliminated. Simulation results demonstrate that, under the same forward conduction voltage (VON) condition, the proposed device exhibits a significantly lower turn-on energy loss (EON) compared to the traditional super junction(SJ-IGBT), and is 44.5% lower than that of IPBJ-IGBT, while their turn-off energy losses (EOFF) are almost equivalent.Besides, the optimized E-field distribution in the SJBJ-IGBT shows 13.2% improvement of BV. Researching results can provide important reference for reducing the ESW of IGBT.

High voltage carrier stored trench bipolar transistor with common anode polysilicon diodes gate structure for low Miller capacitance and low electromagnetic interference noise

A novel 3300 V high voltage carrier stored trench bipolar transistor (CSTBT) with common anode polysilicon diodes gate structure (CAPD-CSTBT) is proposed. The PN junctions and N+ emitter region in the polysilicon gate structure are beneficial for reducing the Miller capacitance by 88.1% and the input capacitance by 26.0%, while due to the polysilicon PN junction barrier, the forward and reverse gate bias voltage will not be affected. As a result, the transient energy loss could be decreased by 32.2% with the same range of R g. Since the displacement current is shielded by the embedded emitter on the bottom of the CAPD gate structure, the (dI CE /dt)max/I Load is lower than that of the Fin-P-CSTBT by 81.8% on average with the same range of turn-on energy loss. Furthermore, the proposed structure features a 58.7% lower (dV KA /dt)max/V cc value for the free-wheeling diode on average. By Fourier transformation, the proposed structure represents lower amplitudes for the I CE and V KA spectrums during the turn-on period, which is a drastic suppression of electromagnetic interference noise.

Prediction Method of Driving Strategy of High-Power IGBT Module Based on MEA-BP Neural Network

An insulated gate bipolar transistor (IGBT) driver is crucial for improving the reliability of a power electronics system. This paper proposes a method for predicting the optimal driving strategy of high-power IGBT module based on backpropagation neural network optimized by the mind evolutionary algorithm in order to solve the problem of compromise among switching loss, switching time and overshoot and achieve a good driving effect. The three regions of switching transitions are analyzed based on the switching characteristics of the IGBT module. Neural networks are established to predict turn-on and turn-off driving strategies for variable gate resistance active gate driver of the IGBT module. The mind evolutionary algorithm is used to optimize the weights and biases of the neural networks so that the optimal weights and biases can be obtained. In order to verify the effectiveness of the driving strategy prediction method proposed in this paper, experiments are carried out for 4500V/900A the IGBT module. Compared to the conventional gate driver, the predicted driving strategies reduce the turn-on energy loss, turn-on time, overcurrent, comprehensive evaluation method, turn-on delay time and tail voltage duration by 59.31%, 46.38%, 36.99%, 65.65%, 1.9 μs, 2.9 μs, respectively. It was also found that the Planar-IGBT turn-off process was rarely affected by the gate resistance. The proposed method in this paper can be used not only for the guidance of the driving strategy determination of high-power the IGBT module driver, but also for the driver circuit improvement in the design process.

An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage ( ${V}_{\textsf {BR}}$ ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time ( ${T}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off time ( ${T}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss ( ${E}_{\mathbf {SW}}$ ).

Simulation Study of a Low Switching Loss FD-IGBT With High <inline-formula> <tex-math notation="LaTeX">$dI/dt$ </tex-math> </inline-formula> and <inline-formula> <tex-math notation="LaTeX">$dV/dt$ </tex-math> </inline-formula> Controllability

In this brief, a novel floating dummy insulated gate bipolar transistor (FD-IGBT) is proposed and investigated by simulation. A floating n region and a p+ region shorted with an emitter in the floating p-base region are introduced to form an open-base transistor, and the voltage of the floating p-base region can be clamped by this transistor. In the turn-ON transient, the pile-up of holes in the floating p-base region increases its quasi-Fermi potential and leads to punch-through of the floating n region at a low voltage, which in turn clamps the voltage of the floating p-base region, decreasing the Miller capacitance and thereby the reverse gate charging current from the floating p-base region to the gate. As a result, the proposed FD-IGBT demonstrates not only dramatically reduced turn-ON energy loss for the lower Miller capacitance but also excellent controllability on $dI_{\text {CE}}$ / dt and $dV_{\text {CE}}$ / dt , and hence on the reverse recovery $dV_{\text {KA}}$ / dt of the free-wheeling diode (FWD) for the lower reverse gate charging current. TCAD simulation results indicate that, for the same ${E}_{ \mathrm{\scriptscriptstyle ON}}+{E}_{ \mathrm{\scriptscriptstyle OFF}}$ of 90.8 mJ/cm2, $dI_{\text {CE}}$ / dt of the proposed IGBT and the reverse recovery $dV_{\text {KA}}$ / dt of FWD are decreased by 87.7% and 58.2%, respectively, compared with the conventional one.

Transient Turn-ON Characteristics of the Fin p-Body IGBT

In this paper, the transient turn-ON performance of the 1200 V-class fin p-body insulated gate bipolar transistor (Fin-p IGBT) is numerically analyzed and experimentally characterized. Analysis shows that the gate self-charging effect at the turn-ON transient of the device can effectively be suppressed due to its unique structural features of wide trenches and spacer gates. As a result, the Fin-p IGBT demonstrates excellent controllability on the turn-ON dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> /dt of the IGBT, and hence the reverse-recovery dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">KA</sub> /dt of the free-wheeling diode. Compared with conventional floating p-body IGBTs, the Fin-p IGBT can achieve a significant reduction (up to 82%) in the reverse-recovery dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">KA</sub> /dt, which is of great merit in suppressing the electromagnetic interference noise. Moreover, the turn-ON energy loss of the Fin-p IGBT can be reduced by 53% compared with that of the conventional one at the same reverse-recovery dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">KA</sub> /dt of 10 kV/μs.

Remained p‐GaN effect to turn‐off energy loss ( E off ) in p‐GaN gate power devices

In p-GaN gate AlGaN/GaN power devices, the p-GaN etching process to define the gate region is critical to device performance. In some cases, the remained p-GaN in the ungated region can exist as a result of under-etching, and can act like a charge reservoir in the p-GaN gate power device. In this reported work, the effect of this remained p-GaN layer is investigated for the first time. The main effect of the thick remained p-GaN on the ungated region is the increments of turn-off energy loss (E off) in spite of the similar turn-on energy loss (E on). This is related to the hole trapping in the remained p-GaN region which is observed by the change of turn-off gate voltages.

High-Speed Drive Circuit with Separate Source Terminal for 600 V / 40 A Normally-off SiC-JFET

When using JFETs with a threshold voltage lower than 2 V in a power supply system or inverter system, a high-speed drive circuit capable of precisely controlling the gate current and a mounting method are important to reduce the switching loss. In this paper, a drive circuit of a normally-off SiC-JFET with a separate source terminal is proposed and the effects are evaluated. By dividing the common source inductance and applying the speed-up capacitor, the turn-on time and turn-on energy losses can be decreased by 40% and 60%, respectively. A speed-up capacitor larger than 100 nF greatly decreases the rising time (tr) and turn-on energy losses. By applying the developed normally-off SiC-JFETs and proposed gate driver to PFC circuits and DC/DC circuits, a highly efficient power supply will be achieved.

5 kV, 9.5 A SiC JBS Diodes with Non-Uniform Guard Ring Edge Termination for High Power Switching Application

4H-SiC Junction Barrier Diodes (JBS) diodes were designed, fabricated and tested. The JBS diodes based on a 45μm thick, 1.4×1015cm-3 doped drift layer with multiple non-uniform spacing guard ring edge termination showed a blocking voltage of over 5kV. The 5kV JBS diode has a forward current density of 108A/cm2 at 3.5V and a specific on resistance (RSP_ON) of 25.2mW·cm2, which is very close to the theoretical RSP_ON of 23.3mΩ·cm2. DC I-V measurement of packaged JBS diodes showed a forward current of 100A at a voltage drop of 4.3V. A half-bridge inverter with a bus voltage up to 2.5kV was used to characterize the high power switching performance of SiC JBS diodes. A large inductance load of 1mH was used to simulate the load of a high power AC induction motor. Compared to a Si PIN diode module, the SiC JBS package reduces diode turn-off energy loss by 30% and Si IGBT turn-on energy loss by 21% at room temperature.

2.5KV-30A Inductively Loaded Half-Bridge Inverter Switching using 4H-SiC MPS Free-Wheeling Diodes

2.5KV-30A Inductively Loaded Half-Bridge Inverter Switching using 4H-SiC MPS Free-Wheeling Diodes