Turbo Decoding Algorithms Research Articles

A Parallel Turbo Decoder Based on Recurrent Neural Network

A neural network-based decoder, based on a long short-term memory (LSTM) network, is proposed to solve the problem that large decoding delay and performance degradation under non-Gaussian noise due to poor parallelism of existing turbo decoding algorithms. The proposed decoder refers to a unique component coding concept of turbo codes. First, each component decoder is designed based on an LSTM network. Next, each layer of the component decoder is trained, and the trained weights are loaded into the turbo code decoding neural network as initialization parameters. Then, the turbo code decoding network is trained end-to-end. Finally, a complete turbo decoder is realized. The structural advantage of turbo code component coding is fully considered in the design process, and the problem of decoding delay caused by the existence of interleaver is cleverly avoided. The introduction of deep learning technology provides a new idea to solve the traditional communication problems. Simulation results show that the performance of the proposed decoder is improved by 0.5–1.5 dB compared with the traditional serial decoding algorithm in Gaussian white noise and t-distribution noise. When BER performance is close, the LSTM decoder requires half or even less than that of BCJR. Moreover, the results demonstrate that the proposed decoder is adaptive and can be applied to communication systems with various turbo codes. The LSTM decoder shows lower bit error rate, computational complexity and higher decoding efficiency under the same conditions. Therefore, it is necessary to study the turbo code decoding technology based on deep learning combined with the actual channel environment.

An Efficient Turbo Decoding and Frequency Domain Turbo Equalization for LTE Based Narrowband Internet of Things (NB-IoT) Systems.

This paper addresses the main crucial aspects of physical (PHY) layer channel coding in uplink NB-IoT systems. In uplink NB-IoT systems, various channel coding algorithms are deployed due to the nature of the adopted Long-Term Evolution (LTE) channel coding which presents a great challenge at the expense of high decoding complexity, power consumption, error floor phenomena, while experiencing performance degradation for short block lengths. For this reason, such a design considerably increases the overall system complexity, which is difficult to implement. Therefore, the existing LTE turbo codes are not recommended in NB-IoT systems and, hence, new channel coding algorithms need to be employed for LPWA specifications. First, LTE-based turbo decoding and frequency-domain turbo equalization algorithms are proposed, modifying the simplified maximum a posteriori probability (MAP) decoder and minimum mean square error (MMSE) Turbo equalization algorithms were appended to different Narrowband Physical Uplink Shared Channel (NPUSCH) subcarriers for interference cancellation. These proposed methods aim to minimize the complexity of realizing the traditional MAP turbo decoder and MMSE estimators in the newly NB-IoT PHY layer features. We compare the system performance in terms of block error rate (BLER) and computational complexity.

On the Logical Computational Complexity Analysis of Turbo Decoding Algorithms for the LTE Standards

Evaluating the computational complexity of decoders is a very important aspect in the area of Error Control Coding. However, most evaluations have been performed based on hardware implementations. In this paper, different decoding algorithms for binary Turbo codes which are used in LTE standards are investigated. Based on the different mathematical operations in the diverse equations, the computational complexity is derived in terms of the number of binary logical operations. This work is important since it demonstrates the computational complexity breakdown at the binary logic level as it is not always evident to have access to hardware implementations for research purposes. Also, in contrast to comparing different Mathematical operations, comparing binary logic operations provides a standard pedestal in view to achieve a fair comparative analysis for computational complexity. The usage of the decoding method with fewer number of binary logical operations significantly reduces the computational complexity which in turn leads to a more energy efficient/power saving implementation. Results demonstrate the variation in computational complexities when using different algorithms for Turbo decoding as well as with the incorporation of Sign Difference Ratio (SDR) and Regression-based extrinsic information scaling and stopping mechanisms. When considering the conventional decoding mechanisms and streams of 16 bits in length, Method 3 uses 0.0065% more operations in total as compared to Method 1. Furthermore, Method 2 uses only 0.0035% of the total logical complexity required with Method 1. These computational complexity analysis at the binary logical level can be further used with other error correcting codes adopted in different communication standards.

Turbo codes for telemedicine applications

Telemedicine is an emerging technology in the area of remote medical services. It involves real-time communication between patients and healthcare providers through electronic equipment for diagnosing diseases. Biomedical signal processing is the process of measurement and analysis to deliver required information for doctors to make decisions. The identification of diseases is made upon collecting the biomedical signals from the patient’s body. Telemedicine concepts can be employed for this method. For remote diagnosis purposes, as the biomedical signal needs to transmitted through wireless media there is a need for efficiently coding them. In this paper, turbo coding is used and is transmitted through the AWGN channel. The performance of BER for different turbo decoding algorithms are compared to obtain error free transmission.

Recurrent neural network based turbo decoding algorithms for different code rates

Application of deep learning to error control coding is gaining special attention and neural network architectures on decoding are approached to compare with conventional ones. Turbo codes conventionally use BCJR algorithm for decoding. In this paper, performances of neural Turbo decoder and deep learning-based Turbo decoder are examined. A category of sequential codes are utilized to construct the RSC (Recursive Systematic Convolutional) codes as basic elements for Turbo encoder. Sequential codes suit the requirement of memory element present in convolution codes, which act as components for Turbo encoder. Turbo decoders are constructed by two means; as neural Turbo decoder and deep learning Turbo decoder. Both structures are based on recurrent neural network (RNN) architectures. RNN architectures are preferred due to the presence of memory as a feature. BER performance of both is compared with that of a convolutional Viterbi decoder in awgn channel. Both the structures are studied for different input data-lengths and code rates.

Attenuation Factor approach to minimize the correlation effect in Soft Output Viterbi Algorithm

Prominent turbo decoding algorithms used for wireless applications are Maximum A posteriori Probability (MAP) and Soft Output Viterbi Algorithm (SOVA). These algorithms are known for their error correcting performance close to Shannon’s limit. MAP algorithm is intense in terms of computational complexity but gives optimal performance. SOVA algorithm gives sub-optimal performance with reduced complexity and is appropriate for real time implementation. Sub-optimal performance of SOVA is attributed to correlation effect that exists between intrinsic and extrinsic information exchanged between component turbo decoders. This paper aims at reducing the correlation effect in SOVA using Attenuation Factor (AF) approach. In this approach, two AF values are selected through MATLAB simulation that minimizes the correlation between intrinsic and extrinsic information of the two constituent decoders. Acquired AF values are analysed in Additive White Gaussian Noise (AWGN) and Rayleigh fading channel. To justify the efficiency of the proposed SOVA algorithm, EXIT chart analysis, BER analysis and complexity analysis are done. The results depict that the proposed AF approach reduces the correlation effect in SOVA with nominal BER and complexity.

Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE

In order to meet the latency requirements of the ultra-reliable low latency communication (URLLC) mode of the third-generation partnership project’s long term evolution (LTE) mobile communication standard, this paper proposes a novel turbo decoding algorithm that supports an arbitrarily high degree of parallel processing, facilitating significantly higher processing throughputs and substantially lower processing latencies than the state-of-the-art (SOTA) LTE turbo decoder. As in conventional turbo decoding algorithms, the proposed Arbitrarily Parallel Turbo Decoder (APTD) decomposes each frame of information bits into a sequence of windows, where the bits within different windows are processed simultaneously using forward and backward recursions in a serial manner. However, in contrast to conventional turbo decoding algorithms, the APTD does not require different windows to be composed of an identical number of bits, which allows the use of an arbitrary number of windows and hence an arbitrary degree of parallelism, when decoding information bits of an arbitrary frame length. Furthermore, conventional turbo decoding algorithms alternate between simultaneously processing the windows in the upper decoder and those in the lower decoder. By contrast, the APTD processes the odd-indexed windows in the upper decoder at the same time as the even-indexed windows in the lower decoder and alternates between this and the reversed arrangement, hence further improving the decoding throughput and latency. Furthermore, the APTD achieves a reduced hardware resource requirement by calculating the extrinsic information based only on the outputs of the forward recursions, rather than based on both the forward and backward recursions of conventional turbo decoding algorithms. We demonstrate that the proposed APTD achieves superior latency, throughput, and computational efficiency than the SOTA LTE turbo decoder at all frame lengths, but particularly at the short frame lengths that are typically used in URLLC approaches. For example, at a frame length of $N={504}$ bits, the proposed APTD achieves an FER of 10−5 at the same $E_{b}/N_{0}$ as $I=8$ iterations of a conventional turbo decoder but with a computational efficiency that is 6 times higher than that of the SOTA turbo decoder, while achieving a latency and throughput that are 0.7 and 1.4 times those of the SOTA decoder, respectively.

Efficient decoding algorithm for 3D video over wireless channels

In wireless communication networks, additive channel noise and time varying multipath fading are considered amongst the main challenges and these effects will bring significant quality degradation to the transmitted 2D/3D video streams. This paper presents an efficient decoding algorithm for Distributed Video Coding (DVC) for enhanced performance of colour and depth based 3D video over error prone wireless channels. The maximum a-posteriori (MAP) algorithm for turbo decoding is modified considering the effects of the channel errors on both Wyner-Ziv and key frame bit streams of colour and depth videos. The proposed codec is simulated using a W-CDMA wireless channel model and the results are analyzed to determine the effect of the modifications. The performance of the state-of-the-art H.264/AVC video codec is also presented for comparison under similar conditions. The results show that the proposed modifications provide a significant improvement in the DVC codec performance under unfavourable channel conditions for colour plus depth based 3D video.

Throughput enhancement of SISO parallel LTE turbo decoders using floating point turbo decoding algorithm

The floating point decoding algorithm for advanced turbo decoders is proposed in this paper. The analysis of the proposed algorithm is done as an alternative to the Tail Over-Lapped Decoding (TOD) algorithm. This article is described as a comparative analysis of the TOD and floating point turbo decoding algorithm for the throughput enhancement of the fourth generation mobile networks. The latter one is proved to be better for the throughput enrichment and latency reduction with reduced power consumption for Long Term Evolution (LTE) networks. The decoder with odd-even interleaver considerably reduces the computational complexity and thus enhances the throughput.

Throughput enhancement of SISO parallel LTE turbo decoders using floating point turbo decoding algorithm

The floating point decoding algorithm for advanced turbo decoders is proposed in this paper. The analysis of the proposed algorithm is done as an alternative to the Tail Over-Lapped Decoding (TOD) algorithm. This article is described as a comparative analysis of the TOD and floating point turbo decoding algorithm for the throughput enhancement of the fourth generation mobile networks. The latter one is proved to be better for the throughput enrichment and latency reduction with reduced power consumption for Long Term Evolution (LTE) networks. The decoder with odd-even interleaver considerably reduces the computational complexity and thus enhances the throughput.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl–Cocke-Jelinek–Raviv (Log-BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time wireless communication schemes. Motivated by this, we recently proposed a fully parallel turbo decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for field-programmable gate array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gb/s and an average latency of 0.56 $\mu \text{s}$ , when decoding frames comprising ${N}=720$ b. These are, respectively, 13.2 times and 11.1 times superior to those of the state-of-the-art FPGA implementation of the Log-BCJR long-term evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 (kALUTs/Mb/s), which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest $N=40$ -b LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mb/s and an average latency of 0.18 $\mu \text{s}$ , which are, respectively, 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 (kALUTs/Mb/s) is 146.4 times superior to that of the benchmarker decoder.

VLSI Implementation of Fully Parallel LTE Turbo Decoders

Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having $E_{b}/N_{0}=1~ \text {dB}$ , the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of $0.28~ \mu \text {s}$ . These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of $2.69~ \mu \text {J}$ /frame and a normalized core area of $5~ \text {mm}^{\vphantom {R^{'}}2}/\text {Gb/s}$ , which are 34% and 23% lower than those of the benchmarker, respectively.

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit

Turbo codes comprising a parallel concatenation of upper and lower convolutional codes are widely employed in the state-of-the-art wireless communication standards, since they facilitate transmission throughputs that closely approach the channel capacity. However, this necessitates high processing throughputs in order for the turbo code to support real-time communications. In the state-of-the-art turbo code implementations, the processing throughput is typically limited by the data dependences that occur within the forward and backward recursions of the Log-BCJR algorithm, which is employed during turbo decoding. In contrast to the highly serial Log-BCJR turbo decoder, we have recently proposed a novel fully parallel turbo decoder (FPTD) algorithm, which can eliminate the data dependences and perform fully parallel processing. In this paper, we propose an optimized FPTD algorithm, which reformulates the operation of the FPTD algorithm so that the upper and lower decoders have identical operation, in order to support single instruction multiple data operation. This allows us to develop a novel general purpose graphics processing unit (GPGPU) implementation of the FPTD, which has application in software-defined radios and virtualized cloud-radio access networks. As a benefit of its higher degree of parallelism, we show that our FPTD improves the higher processing throughput of the Log-BCJR turbo decoder by between 2.3 and 9.2 times, when employing a high-specification GPGPU. However, this is achieved at the cost of a moderate increase of the overall complexity by between 1.7 and 3.3 times.

A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation

Matlab codes relating to the article Al-Dujaily, Ra'ed, Li, An, Maunder, Robert G, Mak, Terrence, Al-Hashimi, Bashir M. and Hanzo, Lajos (2016) A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation. IEEE Access.

Multimode Radix-4 SISO Kernel Design for Turbo/LDPC Decoding

To increase the quality of wireless transmission, wireless communication systems employ advanced forward error correction codes such as turbo codes and low-density parity-check (LDPC) codes. To achieve smooth transition between turbo and LDPC decoding in different communication standards, we propose a VLSI design of a multimode radix-4 soft-input soft-output (SISO) kernel in this paper. The proposed radix-4 SISO kernel composed of three recursive processing elements alternatively employs a radix-4 forward–backward algorithm for LDPC decoding and a radix-4 single-binary/double-binary enhanced max-log-maximum a posteriori probability algorithm for turbo decoding by efficiently sharing computational units. The proposed radix-4 SISO kernel achieves an area reduction of 21.8% when compared with the uncombined SISO kernels for alternatively decoding the turbo and LDPC codes. The proposed radix-4 SISO kernel is verified by implementing it in an application-specific integrated circuit of 0.45 $\mathrm{mm}^{2}$ core area by using a 90-nm CMOS process with a maximum area efficiency of 10.65 bits/ $\mathrm{mm}^{2}$ . In addition, the throughput rates of the long-term evolution and worldwide interoperability for microwave access schemes for both LDPC and turbo decoding can be achieved using eight proposed radix-4 SISO kernels.

A Fully-Parallel Turbo Decoding Algorithm

This paper proposes a novel alternative to the Logarithmic Bahl-Cocke-Jelinek-Raviv (Log-BCJR) algorithm for turbo decoding, yielding significantly improved processing throughput and latency. While the Log-BCJR processes turbo-encoded bits in a serial forwards-backwards manner, the proposed algorithm operates in a fully-parallel manner, processing all bits in both components of the turbo code at the same time. The proposed algorithm is compatible with all turbo codes, including those of the LTE and WiMAX standards. These standardized codes employ odd-even interleavers, facilitating a novel technique for reducing the complexity of the proposed algorithm by 50%. More specifically, odd-even interleavers allow the proposed algorithm to alternate between processing the odd-indexed bits of the first component code at the same time as the even-indexed bits of the second component, and vice-versa. Furthermore, the proposed fully-parallel algorithm is shown to converge to the same error correction performance as the state-of-the-art turbo decoding algorithm. Owing to its significantly increased parallelism, the proposed algorithm facilitates throughputs and latencies that are up to 6.86 times superior to those of the state-of-the art algorithm, when employed for the LTE and WiMAX turbo codes. However, this is achieved at the cost of a moderately increased computational complexity and resource requirement.

Fast Converging Generalized Turbo Decoding Scheme with Enhanced Throughput for Mobile Radio

The use of turbo codes enhances the data transmission efficiency and optimizes the performance of a communication system over wireless fading channels. In this paper, we present a brief overview of the various components of the turbo coding scheme, analyze the complexities of the most popular turbo decoding algorithms, and discuss the various implementation methods of the maximum a posteriori (MAP) algorithm. The paper considers the well-known log-MAP decoding algorithm by a linear approximation of the correction function used by the max* operator. We propose a generalized decoding scheme that optimizes the existing MAP algorithm for faster convergence and better throughput on the basis of varying channel conditions. The proposed scheme of decoding reduces complexity and enhances the throughput with only a negligible loss in BER performance.

Non-recursive max∗ operator with reduced implementation complexity for turbo decoding

In this study, the authors deal with the problem of how to effectively approximate the max* operator when having n>2 input values, with the aim of reducing implementation complexity of conventional Log-MAP turbo decoders. They show that, contrary to previous approaches, it is not necessary to apply the max* operator recursively over pairs of values. Instead, a simple, yet effective, solution for the max* operator is revealed having the advantage of being in non-recursive form and thus, requiring less computational effort. Hardware synthesis results for practical turbo decoders have shown implementation savings for the proposed method against the most recent published efficient turbo decoding algorithms by providing near optimal bit error rate (BER) performance.

고속 전력선 통신을 위한 터보 부호화된 OFDM

본 논문은 전력선 통신 채널에서 터보 부호와 OFDM 시스템의 성능을 분석하고 시뮬레이션 하였다. 전력선통신 시스템은 최악의 환경에서 동작되기 때문에 터보 부호는 전송 데이터의 신뢰성을 보장하기 위해서 사용되었다. 시뮬레이션의 성능은 비트 오류 확률로써 표현하였다. 터보 복호 알고리즘으로써 MAP과 Max-Log MAP 알고리즘, 그리고 SOVA를 선택하였고, 이것들의 성능을 비교하였다. 시뮬레이션 결과로부터, Max-Log MAP 알고리즘이 성능과 복잡도면에서 유망하다는 것이 입증되었다. 그리고 터보 부호기의 인터리버 길이가 100에서 5000으로 변할 때와 반복 횟수가 2번에서 8번으로 증가할 때, 각 각 3dB증가하였음을 알 수 있다. 본 논문에서의 결과는 OFDM를 기반으로 하는 전력선 통신 시스템에 적용될 수 있음을 보여준다. In this paper, performance of a turbo-coded OFDM system is analyzed and simulated in a power line communication channel. Since the power line communication system typically operates in a hostile environment, turbo code has been employed to enhance reliability of transmitted data. The performance is evaluated in terms of bit error probability. As turbo decoding algorithms, MAP (maximum a posteriori), Max-Log-MAP, and SOVA (soft decision viterbi output) algorithms are chosen and their performances are compared. From simulation results, it is demonstrated that Max-Log-MAP algorithm is promising in terms of performance and complexity. It is shown that performance is improved 3dB by increasing the number of iterations, 2 to 8, and interleaver length of a turbo encoder, 100 to 5000. The results in this paper can be applied to OFDM-based high-speed power line communication systems.

Unified scaling factor approach for turbo decoding algorithms

Turbo (iterative) decoding can be implemented with a large family of soft-input soft-output (SISO) algorithms, including suboptimal but practical algorithms such as the soft-output Viterbi algorithm (SOVA) and max-log-MAP algorithm. The performance with these practical algorithms can be improved with simple scaling factor methods. However, their theoretical analysis was mainly based on the relaxed assumption proposed by Papke et al. that the extrinsic information is Gaussian distributed. This study proposes a novel scaling factor approach for reducing both the overestimation of reliability values and the correlation between the intrinsic and extrinsic information. Explicit formulae for computing the scaling factors are derived based on mathematical statistics. A key difference compared to the scaling factor method of Papke et al. is that the proposed scaling factors can be computed off-line. The numerical results show that when implemented in the decoding algorithm of block component codes, the proposed scaling factor approach improves the performance of turbo decoding over additive white Gaussian noise and Rayleigh fading channels. It is superior than the method by Papke et al. in both performance and complexity.