Multimode Radix-4 SISO Kernel Design for Turbo/LDPC Decoding

Abstract

To increase the quality of wireless transmission, wireless communication systems employ advanced forward error correction codes such as turbo codes and low-density parity-check (LDPC) codes. To achieve smooth transition between turbo and LDPC decoding in different communication standards, we propose a VLSI design of a multimode radix-4 soft-input soft-output (SISO) kernel in this paper. The proposed radix-4 SISO kernel composed of three recursive processing elements alternatively employs a radix-4 forward–backward algorithm for LDPC decoding and a radix-4 single-binary/double-binary enhanced max-log-maximum a posteriori probability algorithm for turbo decoding by efficiently sharing computational units. The proposed radix-4 SISO kernel achieves an area reduction of 21.8% when compared with the uncombined SISO kernels for alternatively decoding the turbo and LDPC codes. The proposed radix-4 SISO kernel is verified by implementing it in an application-specific integrated circuit of 0.45 $\mathrm{mm}^{2}$ core area by using a 90-nm CMOS process with a maximum area efficiency of 10.65 bits/ $\mathrm{mm}^{2}$ . In addition, the throughput rates of the long-term evolution and worldwide interoperability for microwave access schemes for both LDPC and turbo decoding can be achieved using eight proposed radix-4 SISO kernels.