Turbo Decoder Architecture Research Articles

Design of a modified Bi-directional SOVA

In this paper, a directional bi-directional Soft-Output Viterbi algorithm (SOVA) based Turbo decoder architecture is proposed. By performing an extra pass through the decoder trellis, effectively b...

Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s

This paper presents a new circuit architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our full-parallel architecture is that it enables the memory block between each half-iteration to be removed. In fact, the proposed architecture opens the way to numerous applications such as optical transmission. In particular, our block turbo decoding architecture can support optical transmission at data rates above Gbit/s

Full-parallel architecture for turbo decoding of product codes

A full-parallel architecture for turbo decoding, which achieves ultra-high data rates when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed-Solomon component codes. The major advantage of our architecture is that it enables the memory blocks between all half-iterations to be removed. Moreover, the latency of the turbo decoder is strongly reduced. The proposed architecture opens the way to numerous applications such as optical transmission and data storage. In particular, the block turbo decoding architecture can support optical transmission at data rates above 10 Gbit/s.

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.

Mapping Interleaving Laws to Parallel Turbo Decoder Architectures

For high data rate applications, the implementation of iterative turbo-like decoders requires the use of parallel architectures posing some collision-free constraints to the reading/writing process in the soft-input soft-output (SISO) decoders. Contrary to the literature belief, we prove in this paper that the parallelism constraints can be met by any permutation law employed by the turbo-interleaver, and we give a constructive method to satisfy those constraints.

Integrated circuits for channel coding in 3G cellular mobile wireless systems

Error control coding is a key element of any digital wireless communication system, minimizing the effects of noise and interference on the transmitted signal at the physical layer. In 3G mobile cellular wireless systems, error control coding must accommodate both voice and data users, whose requirements vary considerably in terms of latency, throughput, and the impact of errors on the user application. At the base station, dedicated hardware or readily reconfigurable components are needed to address the concurrent coding and decoding demands of a large number of users with different call parameters. In contrast, the encoder and decoder at the user equipment (UE) are dedicated to a single call setup which changes infrequently. In designing encoder and decoder solutions for 3G wireless systems, not only are the performance issues important, but also the costs. Cellular wireless infrastructure manufacturers need to reduce costs, maximize system reuse, and increase flexibility in order to compete in the market. Furthermore, future-proofing a network is a primary concern due to the high cost of deployment. For the UE, power consumption (battery life) and size are key constraints in addition to manufacturing costs. This article considers the 3G decoder design problem and, using case studies, describes two 3G decoder solutions using ASICs. The first device is targeted for base station deployment and is based on a unified architecture for convolutional and turbo decoding. The second device is a dedicated high-speed radix-4 logMAP turbo decoder targeted for UE, motivated by the requirements for high-speed downlink packet access. Both devices have been fabricated in 0.18 μm CMOS technology, and while optimized for either base station or UE, may be used in both applications.

Area-efficient high-speed decoding schemes for turbo decoders

Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.

A novel turbo decoder architecture for hand-held communication devices

Mobile communication systems, such as IMT-2000, adopt turbo codes because they provide reliable, bandwidth-efficient communication over AWGN channels. The BER of turbo codes is close to the Shannon limits. As a mobile communication device can use only a limited power supply, use of low power design techniques is essential for successful device implementation. This paper proposes an architecture for the turbo decoder which adopts a fast decoding structure by initial threshold setting such that the number of decoding iterations can be reduced without BER performance degradation. The proposed decoding structure can be easily modified for other MAP decoders by employing a simple decision module. The initial iteration threshold has been decided via simulations by varying decoder parameters (mean/normalized-variance of the log-likelihood ratio; BER of the decoder outputs). Performance validations for the proposed decoder have been performed under the IMT-2000 high-speed data transmission testbed with the channel characteristic being set to BER=10/sup -6/. Simulation results show 55%-90% reductions in the number of decoding iterations when compared with conventional turbo decoders with a fixed number of iterations.

Performance of timing recovery methods in turbo coded magnetic recording channels

Turbo codes, with potential for 5 dB coding gain over the conventional Viterbi detection schemes, are good candidates for the next generation detection/decoding schemes for magnetic recording systems. In this paper, timing recovery is included in the evaluation of turbo codes. Three timing recovery methods, namely voltage control oscillator (VCO) method, interpolated timing recovery (ITR) method and adaptive filter timing recovery (AFTR) method are examined for two turbo decoder architectures, full turbo and serial turbo. Bit error rate (BER) results from simulations suggest that full turbo decoder is more robust than the serial turbo decoder. For serial turbo decoder, error floor is seen earlier in VCO and ITR methods than AFTR methods. Using s-random interleaver seems to be able to remove such an error floor.