Turbo Decoder Architecture Research Articles

Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders

In this brief, a methodology to compare high-throughput turbo decoder architectures, is proposed. The model is based on the area-efficiency estimation of different architectures and design choices. Moreover, it is specifically oriented to the exploration of Parallel-MAP (PMAP) architectures, combined with both the Max-Log-MAP algorithm and the recently proposed Local-SOVA. The main objective is the search for optimal radix-orders, capable to maximize the area-efficiency of the decoder. In this scenario, it is proved that i) radix-orders higher than 4 are expected to drastically reduce the area-efficiency; ii) the optimal choice between radix-2 and radix-4 architectures strongly depends on the area distribution between logic and memory.

CCSDS 131.2-B-1 Serial Concatenated Convolutional Turbo Decoder Architecture for Efficient FPGA Implementation

Most of the turbo encoding schemes at standards are parallel-based, so different architectures for efficient implementation are common in the literature. However, a serial turbo decoder is not that common. This scheme is used in CCSDS 131.2-B-1 standard, which is attracting much of attention recently due to its higher performance for satellite communications. In this paper, an efficient architecture for the decoder is proposed and analyzed. It is intended to show an architecture that can be modeled in a circuit description language (such as VHDL and Verilog) in such a way that it can be easily implemented on a Field Programmable Gate Array (FPGA). This work describes in detail this architecture explaining the encoding operations that are performed at the transmitter and then, how to undo them at the receiver. The proposed algorithm works by using independent components to divide the tasks and to obtain a pipeline architecture to improve the efficiency. The results of simulating and implementing the proposed architecture on a Xilinx Zynq UltraScale+ RFSoC ZCU28DR board with XCZU28DR-2FFVG1517E RFSoC are shown. The final results presented demonstrate how the hardware operations give equivalent results to the software simulation and do not consume board resources aggressively as usually the turbodecoder does.

Reverse Calculation-Based Low Memory Turbo Decoder for Power Constrained Applications

Turbo codes are a family of near Shannon limit error correction coding schemes that usually are adopted for wireless data transmission. To reduce the power dissipation of a long-term evolution (LTE) advanced turbo decoder, in this paper, we propose a reverse calculation based low memory turbo decoder architecture by partitioning the trellis diagram and simplifying the max* operator. The designed forward state metrics calculation architecture is merged with two classical decoding schemes. Through field programmable gate array (FPGA) hardware implementation, the state metrics cache (SMC) capacity is reduced by 65%, the power dissipation of the reverse calculation architecture is significantly reduced for all tested clock frequencies, and the decoding performance is not affected as compared with classical decoding schemes. The proposed reverse calculation architecture is an effective technique to achieve better decoding performance for power-constrained applications.

Evolution of Wireless Communication along with Encoders

Now a days technology drastically increasing, leads to increase in communication also. Internet of Things (IOT) is very basic fundamental necessary to the consumers in this decade, which requires a communication path mainly from end to end. By understanding this technology growth, took as motivation and started a survey for turbo decoder architecture in Long Term Evolution (LTE) and 3GPP-LTE communication. Different generation technologies adopt different kinds of encoder as well as decoder to encrypt the data which can be sent from source devices to destination devices, which consists parameters like data rate, frequency used to transmit and speed of transitioning i.e., encoding and decoding the data at the transmitter as well as receiver. This paper represents a survey on different architectures of turbo decoder in LTE communication which can give a brief idea about the communication and also the usage of turbo encoder in various applications. Initially we look back a history and development of a communication system till LTE. Later we discuss the different technologies and topologies on turbo decoder along with its architecture, advantage and disadvantage.

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding

The multiplication of connected devices goes along with a large variety of applications and traffic types needing diverse requirements. Accompanying this connectivity evolution, the last years have seen considerable evolutions of wireless communication standards in the domain of mobile telephone networks, local/wide wireless area networks, and Digital Video Broadcasting (DVB). In this context, intensive research has been conducted to provide flexible turbo decoder targeting high throughput, multi-mode, multi-standard, and power consumption efficiency. However, flexible turbo decoder implementations have not often considered dynamic reconfiguration issues in this context that requires high speed configuration switching. Starting from this assessment, this paper proposes the first solution that allows frame-by-frame run-time configuration management of a multi-processor turbo decoder without compromising the decoding performances.

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding

The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances.

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

Cyclic Redundancy Check (CRC) is often employed in data storage and communications to detect errors. The 3GPP-LTE wireless communication standard uses a 24-bit CRC with every turbo coded frame, thus, the CRC can be exploited to detect residual errors and to enable early stopping of iterations as well. The current state of the art lacks specific CRC implementations for this standard, and most current solutions adopt a fixed degree of parallelism, unsuitable for many turbo decoder architectures. This work proposes a variable parallelism circuit targeting the 3GPP-LTE/LTE-Advanced 24-bit CRC, that can adapt to input data of different sizes. Low complexity is achieved through careful functional sharing among the various parallelisms: comparison with the state of the art shows comparable or superior speed and extremely low complexity.

Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder

This paper presents hardware and bit-error-rate (BER) performance analysis of simplified maximum-a-posteriori (MAP) algorithms based on piece-wise-linear-approximations and Maclaurin-series-expansion for the turbo codes. From this comparative study, a simplified MAP algorithm with optimal BER performance is selected and an architecture suitable for high speed application is suggested for the design of soft-input-soft-output (SISO) unit. Subsequently, a quantitative model is proposed for estimating the amount of memory required by SISO unit in terms of sliding window size, data width of internal metrics and total number of systematic and parity bits. Thereafter, a non-parallel-radix-2 architecture of turbo decoder which incorporates SISO unit and quadratic-permutation-polynomial interleaver is presented. Application-specific-integrated-circuit (ASIC) implementation of this turbo decoder is carried out in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology node and its power consumption, design area and operating clock frequency are reported. Finally, a comparison with similar contributions in the literature has shown that the implemented turbo decoder achieves energy efficiency of 0.28 nJ/b/iteraions. Similarly, it has achieved a highest throughput of 28 Mbps among radix-2 and radix-4 non-parallel turbo decoders.

Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA+/LTE/LTE-Advanced multi-standard turbo decoder with a 45nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm^2. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards.

Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach

Turbo codes (TCs) have been proposed to reduce the required transmission energy in wireless sensor networks (WSNs), although this gain must be offset by the turbo decoder's processing energy consumption (EC). Previously, it has not been possible to estimate this processing EC until a relatively late stage in the TC design process. This has prevented the consideration of processing EC at the early design stages, when there is the greatest opportunity to adjust the parameters of the design. To address this, we propose a generalized turbo decoder architecture that supports a wide variety of parameters and a framework to estimate its EC as a function of these parameters at an early design stage. We demonstrate that this facilitates a holistic optimization of the TC parameters, minimizing the sum of both the transmission and processing EC.

Improving Network-on-Chip-based Turbo Decoder Architectures

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support double-binary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 dB.

An FPGA realization of simplified turbo decoder architecture

The key issue of applying Turbo codes is to find an efficient implementation of turbo decoder. This paper addresses the implementation of a simplified and efficient turbo decoder in field programmable gate array (FPGA) technology. A simplified and efficient implementation of a Turbo decoder with minor performance loss has been proposed. An integer Turbo decoder based on the standard 2’s complement number system after considering the issues of dynamic range, truncation effect and other algorithm related subjects has been introduced. The efficient implementation comes from algorithm modification, integer arithmetic and compact hardware management. Based on the Max-Log-MAP decoding algorithm, the branch metric is modified by weighting a priori value, resulting in a significant BER improvement. The Turbo decoder takes in 8-level integer inputs generates 7-bit soft-decisions and calculates all metrics on integers, avoiding complex floating point or fixed-point arithmetic. By manipulating memory address, delay associated with interleaving and de-interleaving is eliminated, resulting in much higher throughput. Also, by taking advantage of identical decoder function, Turbo decoder is implemented in a single-decoder structure, making efficient use of memory and logic cells. Key words: Turbo, Max-Log-MAP, field programmable gate array, bit error ratio.

State Metric Compression Techniques for Turbo Decoder Architectures

This papers proposes to compress state metrics in turbo decoder architectures to reduce the decoder area. Two techniques are proposed: the first is based on non-uniform quantization and the second on the Walsh-Hadamard transform followed by non-uniform quantization. The non-uniform quantization technique reduces state metric memory area of about 50% compared with architectures where state metric compression is not performed, at the expense of slightly increasing the error correcting performance floor. On the other hand, the Walsh-Hadamard transform based solution offers a good tradeoff between performance loss and memory complexity reduction, which reaches in the best case 20% of gain with respect to other approaches. Both solutions show lower power consumption than architectures previously proposed to compress state metrics.

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures

This paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in the design space are investigated, namely, network topology, parallelism degree, the rate at which messages are sent by processing nodes over the network, and routing strategy. The main results of this analysis are as follows: 1) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de Bruijn and generalized Kautz topologies and 2) depending on the throughput requirements, different parallelism degrees, message injection rates, and routing algorithms can be used to minimize the network area overhead.

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm2 area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm2/Mbps and energy efficiency of 0.55 nJ/b/iter.

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding

Emerging digital communication applications and the underlying architectures encounter drastically increasing performance and flexibility requirements. In this paper, we present a novel flexible multiprocessor platform for high throughput turbo decoding. The proposed platform enables exploiting all parallelism levels of turbo decoding applications to fulfill performance requirements. In order to fulfill flexibility requirements, the platform is structured around configurable application-specific instruction-set processors (ASIP) combined with an efficient memory and communication interconnect scheme. The designed ASIP has an single instruction multiple data (SIMD) architecture with a specialized and extensible instruction-set and 6-stages pipeline control. The attached memories and communication interfaces enable its integration in multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffled decoding technique introduced in the turbo-decoding field to achieve higher throughput. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for all simple and double binary turbo codes of existing and emerging standards. Results obtained for double binary WiMAX turbo codes demonstrate around 250 Mb/s throughput using 16-ASIP multiprocessor architecture.

High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping

Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memory blocks between all half-iterations to be removed is presented. A complexity analysis of the elementary decoder leads to a low complexity decoder architecture for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup which also includes an innovative parallel product encoder. The implemented block turbo decoder processes input data at 600 Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Some solutions to reach even higher data rates are finally presented.

A low complexity block turbo decoder architecture - [transactions letters

In this letter we present a low-complexity architecture designed for the decoding of block turbo codes. In particular we simplify the implementation of Pyndiah's algorithm by not storing any of the concurrent codewords generated by the list decoder.

Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design

Turbo product codes (TPCs) are an attractive solution to improve link budgets and reduce systems costs by relaxing the requirements on expensive optical devices in high capacity optical transport systems. In this paper, we investigate the use of Reed-Solomon (RS) turbo product codes for 40Gbps transmission over optical transport networks and 10Gbps transmission over passive optical networks. An algorithmic study is first performed in order to design RS TPCs that are compatible with the performance requirements imposed by the two applications. Then, a novel ultrahigh-speed parallel architecture for turbo decoding of product codes is described. A comparison with binary Bose-Chaudhuri-Hocquenghem (BCH) TPCs is performed. The results show that high-rate RS TPCs offer a better complexity/performance tradeoff than BCH TPCs for low-cost Gbps fiber optic communications.