Abstract
Turbo codes are a family of near Shannon limit error correction coding schemes that usually are adopted for wireless data transmission. To reduce the power dissipation of a long-term evolution (LTE) advanced turbo decoder, in this paper, we propose a reverse calculation based low memory turbo decoder architecture by partitioning the trellis diagram and simplifying the max* operator. The designed forward state metrics calculation architecture is merged with two classical decoding schemes. Through field programmable gate array (FPGA) hardware implementation, the state metrics cache (SMC) capacity is reduced by 65%, the power dissipation of the reverse calculation architecture is significantly reduced for all tested clock frequencies, and the decoding performance is not affected as compared with classical decoding schemes. The proposed reverse calculation architecture is an effective technique to achieve better decoding performance for power-constrained applications.
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