TFET Research Articles

Design and sensitivity study of a novel Z-shaped gate TFET sensor with SiGe source for chemical analyte detection

In this work, we have designed a chemical gas sensor using a Z-shaped gate tunnel FET with a SiGe source. Here, the gate material is a conducting organic polymer, which allows for the effective detection of a variety of chemical analytes. Over the course of the sensitivity investigation, several chemical analytes were exposed, including hexane, methanol, iso-propanol, and chloroform. Detecting chemical gases is feasible due to the work-function modification of the conducting polymer with exposure to the chemical gas vapors. This leads to modifications in the electrical properties of the suggested gas sensor, which serves as a sensing metric. The impact of surrounding temperature on various sensitivity parameters of the TFET-based gas sensor is also investigated. The proposed heterostructure Z-TFET (ZHS-TFET) offers a peak drain current sensitivity of 5.65 × 105 in the case of chloroform, which is four times higher than the sensitivity provided by the ZTFET sensor. Further, the suggested chemical sensor offers a higher subthreshold swing sensitivity (SSS) of 0.29 and a current ratio sensitivity (Sratio) of 3.18. As a result of its higher-sensitivity nature and improved electrostatic performance, the proposed sensor with conducting polymer as the gate metal may be able to meet the needs of the chemical and pharmaceutical industries, as well as environmental monitoring and biological diagnostics.

A modified gate oxide tunnel Field-Effect transistor (TFET) biosensor to identify receptor Tyrosine-Protein kinase 2 (C-erbB-2) in Serum/Saliva

This research demonstrates an analysis of a modified gate oxide tunnel field-effect transistor (TFET) with pocket (Poc-MGOTFET) biosensor for the incredibly sensitive and real-time identification of the breast cancer (BC) biomarker receptor tyrosine-protein kinase (C-erbB-2) in serum and saliva. This research investigates the impact of interface charge modulation in Poc-MGOTFET biosensor with embedded cavities for rapid, accurate, and reliable identification of antigens in bodily fluids, like serum and saliva. The TCAD Sentaurus is used to numerically simulate the proposed biosensor in 2D. The dual cavity etched underneath the dual gate electrode of the proposed biosensor facilitates biomolecule immobilization. This enhances the ability of biomolecules to regulate the source/channel tunneling rate and the proposed biosensor’s electrical performance metrics. A numerical model is developed for the interface charge equivalent of the C-erbB-2. The sensitivity of the device to different C-erbB-2 concentrations in serum/saliva has been studied. The results of our research demonstrate that Poc-MGOTFET, featuring an extended gate structure, modified gate oxide, and pocket along the source side, reduces the leakage current (ILeakage) and OFF current (IOFF), enhances the probability of tunneling, boosts gate control for a greater ON current (ION) and ION/IOFF ratio, and increases sensitivity. Moreover, increased sensitivity by an order of magnitude 106 results from the effect of interface charges corresponding to varying concentrations of C-erbB-2 biomarkers on the sensitivity of the biosensor (as measured by the ION/IOFF ratio).

Linearity and noise evaluation based analysis of extended source heterojunction double gate tunnel FET

This research work evaluates a performance analysis of heterostructure (SiGe/Si) double gate extended source Tunnel FET (Hetero-ES-TFET) to enhance the analog performance, linearity and noise performance. At the source-channel junction, a Hetero-ES-TFET's source is extended into the channel to increase point and line tunneling in the device. The Hetero-ES-TFET exhibits a high ION/IOFF of 3.57 × 1012 and a maximum cut off frequency fT of 54.19 GHz for optimization of device structural parameters. This analysis is conducted using a calibrated SILVACO, technology computer-aided design (TCAD) simulator. The proposed structure includes evaluation of linearity and noise performance characteristics. Furthermore, a linearity analysis as a figure of merit was conducted for the proposed device under study, including different parameters such as 3rd order intermodulation distortion point (IMD3), 3rd order intermodulation intercept point (IIP3), 2nd and 3rd order voltage intercept point (VIP2 and VIP3). The proposed Hetero-ES-TFET has achieved an incredibly high ON current and low threshold voltage. The effect of increasing source width has been examined in this work while sub-threshold swing (SS) remains unchanged during the analysis. There is an improvement in threshold voltage and ION/IOFF value by using silicon-germanium (SiGe) as a source material.

Design and sensitivity analysis of a vertical TFET with dielectric pocket for its use as label free biosensor

A comprehensive analysis of a dielectrically modulated vertical tunnel field effect transistor (VTFET) as a label free biosensor is presented in this article. The proposed structure considers an n+ pocket at the source /channel interface and a dielectric pocket at channel/drain interface. The sensitivity of the VTFET biosensor has been investigated, introducing neutral and charged biomolecules of different dielectric constants at the nanogap cavity. The n+ doped pocket introduced at the source/channel junction improves the output characteristics of the proposed VTFET due to its conduction mechanism in both lateral and vertical directions, thereby improving the sensitivity of VTFET biosensor as well. The proposed VTFET biosensor gains the sensitivity in the order of 105 for a fully filled cavity. Moreover, the HfO2 dielectric pocket at the channel/drain interface suppresses the deteriorating ambipolar behaviour and also enhances the ambipolar current sensitivity compared to a VTFET biosensor without dielectric pocket. Thus, it is perceived that the main drawback of TFET, ambipolar nature, has evolved as an advantage for sensing applications. The VTFET biosensor has been analyzed with regards to variations in dielectric constant of cavity, density of charge, length and height of cavity, mole fraction and also operating temperature at a particular bias condition to judge its sensing capability. A status map has been presented where the proposed VTFET biosensor has been compared with some of the significant works reported in literature in terms of sensitivity and selectivity.

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Design and analysis of Si-Ge heterostructure tunnel FET biosensors for detection of a wide range of biomolecules in both wet and dry environments

Design and analysis of Si-Ge heterostructure tunnel FET biosensors for detection of a wide range of biomolecules in both wet and dry environments

Cutting-edge vertical tunnel FETs: GaSb/InSb heterojunction source-all-around tunnel FET with I60 of 2.73×10⁻⁴ A/μm and Sub-10 mV/dec SS

This work introduces an innovative Source-All-Around Vertical Tunnel Field-Effect Transistor (SAA-VTFET) design based on III-V semiconductors. The unique combination of a GaSb/InSb heterojunction, a wider tunneling space, and an n+ source pocket significantly enhances band-to-band tunneling (BTBT), leading to exceptional on-current levels. The device architecture utilizes InSb in the source pocket and channel, materials chosen for their properties that enable efficient carrier transport, ultimately boosting overall device performance. Through meticulous optimization, the SAA-VTFET achieves an I60 (Ids at SS = 60mV/dec) of 2.73 × 10−4 A/μm, an exceptionally low off-current of 1.7 × 10−17 A/μm, a low threshold voltage of 0.16 V, an outstanding ION/IOFF Ratio of 1.64 × 1013, and an attractive subthreshold swing (point SS of 4 mV/dec, average SS of 7 mV/dec). These remarkable achievements underscore the SAA-VTFET's potential to surpass conventional TFETs, paving the way for advanced low-power, high-speed electronics.

Comparative Analysis of Symmetrical/Asymmetrical Vertical Electrolyte‐Insulated Semiconductor Tunnel FET for pH Sensor Application

This study investigates symmetrical/asymmetrical vertical electrolyte‐insulated semiconductor Tunnel field effect transistors (TFETs) (SV‐EIS‐TFET/ASV‐EIS‐TFET) for their application as pH biosensors. On the basis of device‐level simulations, the underlying physics of all architectures is explored and the comparative biosensing abilities of pH biosensors are evaluated. A vertical electrolyte Bio‐TFET with overlapping electrodes is presented in this study. The pH response is measured by observing the change in drain current and potential when the pH of the injected solution transitions from a lower to a higher level. As an intrinsic semiconductor material, electrons and holes in the electrolyte represent mobile ions in the solution. The region of the electrolyte has an electron affinity of 1.32 eV, a bandgap of 1.12 eV, and a dielectric constant of 78. Double gate structures raise concerns about correctly aligning the right and left gates because of their sensitivity impact. An analysis of the effect of gate misalignment on biosensor surface potentials, drain currents, and transconductance is presented. Furthermore, pH value ranges of 1–14 are considered for various sensitivity parameters. Simulations are performed using Silvaco TCAD for the SV‐EIS‐TFET and ASV‐EIS‐TFET biosensors.

Investigation of Reliability Issues in a hybrid Extended Dual Source Double Gate Tunnel FET

This paper presents the design and analysis of an enhanced tunnel field-effect transistor (TFET) structure. The proposed structure comprises a dual source and a double gate, aiming to enhance the DC characteristics of the TFET. The dual source concept is used in the structure with two homogeneous gates, which play a major role in boosting the tunneling parameters. It also examines the affectability of source dimensions and drain doping on the performance of the proposed device. Furthermore, we have compared our proposed structure with the single source device. The proposed device after optimization exhibits an extraordinary I ON/I OFF ratio of 2.33 × 1013, with an I OFF of 6.25 × 10−19A/µm, and decent I on of 1.46 × 10−5A/µm along with a subthreshold swing (SS) of 43 mV/dec. The device characteristics have been analyzed in the presence of interface traps. The electrical parameters have been quantified against various types and concentrations of traps. The performance of the proposed device has been compared with the existing TFET structures.

Proposal and evaluation of Mg2Si-based vertical tunnel field effect transistor for enhanced performance

This work investigates the performance of silicon-on-insulator (SOI) based vertical heterojunction tunnel FET with magnesium silicide (Mg2Si) as source material (Mg2Si-VTFET) with silicon-based counterpart (Si-VTFET). The investigation utilizes SILVACO TCAD tool to analyse various metrics including electrical characteristics, radio-frequency performance, linearity, and distortion. Incorporation of low bandgap material at source forms hetero-junction at source-channel interface, thereby reducing the tunneling path and enhancing the tunneling rate of charge carriers. ON-state current (ION) and current switching ratio (ION/IOFF) for Mg2Si-VTFET improves by factor of approximately ∼ 105 and 102 times. Mg2Si-VTFET outperforms Si-VTFET in terms of ION current for low biasing voltages, transconductance (gm), gain-bandwidth-product (GBP), cut-off frequency (fT) and transit-time. However, Mg2Si-VTFET has better linearity and reduced distortions in terms of VIP2 and HD2 metrics. HD2 suppresses by 53.8 % for Mg2Si-VTFET over Si-VTFET. This suggests that Mg2Si-VTFET is better suited for applications requiring low distortion, such as in audio amplifiers or communication systems. Therefore, Mg2Si-VTFET shows strong candidacy over Si based counterpart for low power circuits.

Phonon-assisted charge carriers thermalization in semiconductor Si and metallic silicide NiSi2, CoSi2: A non-adiabatic molecular dynamics study

Recently, the cold source field-effect transistor (CSFET) has emerged as a promising solution to overcome Boltzmann tyranny in its ballistic regime, offering a steep-slope subthreshold swing (SS) of less than 60 mV/decade. However, challenges arise due to scattering, particularly from inelastic scattering, which can lead to significant degradation in SS through cold carrier thermalization. In this study, we delve into the theoretical investigation of the electronic excitation/relaxation dynamic process using the state-of-the-art nonadiabatic molecular dynamics (NAMD) method. The mixed quantum-classical NAMD proves to be a powerful tool for comprehensively analyzing cold carrier thermalization and transfer processes in semiconductor Si, as well as metallic silicides (NiSi2 and CoSi2). The approach of mixed quantum-classical NAMD takes into account both carrier decoherence and detailed balance, enabling the calculation of thermalization factors, relaxation times, scattering times, and scattering rates at various energy levels. The thermalization of carriers exhibits a gradual increase from low to high energy levels. Achieving partial thermalization from the ground state to reach the thermionic current window occurs within a sub-100 fs time scale. Full thermalization across the entire energy spectrum depends sensitively on the barrier height, with the scattering rate exponentially decreasing as the energy of the out-scattering state increases. Notably, the scattering rate of NiSi2 and CoSi2 is two orders of magnitude higher than that of Si, attributed to their higher density of states compared to Si. This study not only provides insights into material design for low-power tunnel field-effect transistors but also contributes valuable information for advancing CSFET in emerging technologies.

Correction: Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

Correction: Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

This work offers a comprehensive analysis of the adverse impact of interface trap charge (ITC) under the influence of temperature variation on a heterostacked (HS) source L-gate tunnel field effect transistor (TFET) having a SiGe pocket. An investigation of both static and radiofrequency (RF) characteristics has been carried out. It appears that ITCs situated at the Si–oxide interface fluctuate the flat-band voltage to alter the various analog/RF parameter characteristics. Uniform ITCs are seen to be less susceptible to degradation in device characteristics. Low-frequency noise (LFN) analysis has also been carried out considering the impact of different trap distributions (uniform and Gaussian) and densities, which are compared. The temperature dependence of LFN has been studied under the influence of different distributed ITCs, and this has rarely been explored. Moreover, a comparative analysis has been made of the device behavior and LFN characteristics of HS L-gate TFET structures with and without a SiGe pocket. Structures with SiGe pockets were found not to be susceptible to noise effects.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power

Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high ION/IOFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher ION/IOFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher ION/IOFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.

Analog and linearity performance analysis of ferroelectric vertical tunnel field effect transistor with and without source pocket

AbstractThis study examines the electrical performance characteristics of a ferroelectric vertical tunnel field‐effect transistor (TFET) with and without a source pocket (Si0.5Ge0.5). The incorporation of Germanium in the source of the TFET aims to enhance the on‐current. The Silvaco TCAD simulation tool is utilized to simulate the proposed structure. To improve device performance, a ferroelectric layer with a vertical length is employed in the gate of the TFET. When the ferroelectric layer partially controls the channel region, device characteristics, such as on‐current and subthreshold swing (SS) can be improved (i.e., ION = 15.21 × 10−5 A/μm, ION/IOFF = 5.03 × 109, and a minimum SS of 20.87 mV/decade at 300 K). This article studied a comparison between ferroelectric vertical TFETs and nonferroelectric vertical TFETs, as well as ferroelectric vertical TFETs with and without source pockets. The comparison is done on the basis of DC and RF parameters. Analysis of this comparison represents that ferroelectric vertical TFET with source pocket has improved characteristics.

Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance

We introduce two novel III-V inverted T-channel vertical line tunnel field-effect transistor (TFET) configurations, leveraging staggered bandgap compound materials. Design D-1 operate s without negative capacitance, while Design D-2 incorporates negative capacitance. Both designs employ area-enhanced gate normal line tunneling with dual-gate impact, utilizing InGaAs and GaAsSb materials to effectively reduce the overall bandgap. The double-area line tunneling, facilitated by the double gate, significantly enhances performance. D-1 exhibits notable improvements, with an ION value reaching 596.55 μA/μm, an ION/IOFF ratio of 2.5 × 108, a minimum subthreshold swing (SS) of 9.75 mV/dec, and an average subthreshold swing (AVSS) of 31.93 mV/dec. Building upon these achievements, D-2 takes a step further by implementing NC through a ferroelectric layer gate stack, significantly increasing the line tunneling rate symmetrically on the left and right channels beneath both gates. This marks the first proposal of double gate area-enhanced line tunneling with negative capacitance in this paper. D-2 demonstrates remarkable performance for future low-power applications.

Performance Characterization and Analytical Modelling of Electrostatic Doped Heterostructure Nanotube Tunnel Field Effect Transistor

Performance Characterization and Analytical Modelling of Electrostatic Doped Heterostructure Nanotube Tunnel Field Effect Transistor

Study of Process Variation in Nanotube Tunnel Field Effect Transistor

In the nanoscale, the process parameters and device dimension variation extensively affect the electrical performance of the device. Therefore, an inclusive study for the prediction of the overall device behavior is extremely necessary. In this manuscript, process variations caused by random dopant fluctuation (RDFs), variation of oxide thickness, and workfunction during fabrication are analyzed in junctionless nanotube TFET. The work quantitatively evaluates the impact of process variability on the various electrical parameters like energy band diagram, electric field, carrier concentration, and drain current of the nanotube TFET structure. The device simulation has been carried out with a 3-D SILVACO ATLAS simulator.