True Single Phase Clock Research Articles

Altering transistor positions: impact on the performance and power dissipation of dynamic latches and flip-flops

Floating nodes is a point of concern in dynamic latches and flip-flops. When floating these nodes are extremely susceptible to noise: their voltage level may get distorted owing to charge coupling with other nodes. The current approach to this problem is to convert these dynamic circuits into semistatic/static ones by using feedback transistors. Increased robustness in semistatic circuits comes at the expense of decreased performance and increased power dissipation. It is demonstrated that simply altering the relative positions of transistors can protect floating nodes from some of the sources of charge coupling. The simulation results show that for a 0.8 /spl mu/m process the proposed technique leads to a significant improvement in both the speed and power dissipation of the true single-phase clocking single and double edge-triggered flip-flops without compromising chip area.

A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V dd 2, decreasing the supply voltage yields a large reduction in power consumption. The main design objectives for these circuits are glitch-free operation and low power consumption at low supply voltage. The proposed D-FF circuit has been compared with previously known circuits and has been shown to provide superior performance. All circuits in this paper have been simulated using HSPICE with a 0.4-μm CMOS technology at a 2-V supply voltage. An analysis of a serial pipeline multiplier design establishes the superiority of the proposed circuit in that application.

New single-clock CMOS latches and flipflops with improved speed and power savings

New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

Logic Synthesis with High Speed CMOS Circuit Techniques

Systems for automated logic synthesis with the True Single Phase Clocking circuit technique (TSPC) and a modified form of the Clock and Data Precharged Dynamic (CDPD) circuit technique, are present...

Fully pipelined TSPC barrel shifter for high-speed applications

In this paper we describe a TSPC (True Single-Phase-Clock) barrel shifter for high-speed, real time applications. The circuit consists of a shift and rotate array and a control unit, both having a pipeline structure, which allows on-line programming. Using 1.5 /spl mu/m CMOS technology, a full custom prototype for 16-b data shift and rotate array has been implemented, with a simplified control unit, and testing circuitry. Worst case HSPICE simulations indicate a maximum operating frequency of over 100 MHz, both for the barrel with on-line programming and for the barrel implemented. The full functionality of the prototype has been tested up to 25 MHz, although each bit path has been tested at 100 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fast VLSI systolic array for large modulus residue addition

The Residue number system (RNS) is inherently suited to high speed computations using custom tailored VLSI systems. In this paper, an algorithm for residue addition, based on a novel, ‘non unique’ number representation scheme, is implemented by a systolic array embedded in a VLSI chip. The pipelined cells are implemented, using a true single phase clock dynamic circuit structure, with computer synthesized minimized trees (switching trees). The array may be easily programmed by the user to accept any arbitrary modulus. Important applications of this array are in residue decoding and fault tolerant computation requiring the use of the Chinese Remainder Theorem where the modulus for addition is relatively large.

Implementation of truesingle-phase clock D flipflops

A D flipflop is a basic element in logic design. The author presents a D flipflop implementation. Unlike a traditional implementation in which two complementary D latches are connected in series, the presented circuit is based on a single stage of precharged cascade differential voltage switch logic (CVSL). The main advantages of the D flipflop are that it has a true single phase clocking scheme, i.e. no clock inversion signal is needed, has a low clock load capacitance, and is glitch free and race free.< >

A 470-MHz CMOS true single-phase clocked bit-serial arithmetic unit

A two's complement bit-serial arithmetic unit (AU) that operates at very high clock rates is presented in this paper. It is designed for a bit-serial SIMD data-path architecture and can perform several different arithmetic operations; for example sum-of-two-products. In order to attain a very high clock rate, the AU circuitry employs the true single-phase clocking (TSPC) technique, which encourages a high degree of pipelining. A 5-bit AU chip on an active area of 0.073 mm/sup 2/ has been fabricated in a 1.0-/spl mu/m standard CMOS process. Tests have verified correct chip operation up to a clock rate of 470 MHz at V/sub dd/=5 V. At this frequency the AU power consumption is 11.5 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 700-MHz 24-b pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator

To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2- mu m CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7-mm*1.7-mm IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pushing the limits of standard CMOS

An improved clocking scheme and sharper circuit design and logic selection, which have yielded a five-to-tenfold increased in the speed of standard CMOS ICs, are discussed. The clocking strategy relies on a true single-phase clock, device sizes are varied to optimize their speed, and a precharged logic style reduces capacitive loads. The tradeoff is roughly a doubling of circuit area. The high-speed CMOS technique has been demonstrated experimentally, with good results. For example, ripple counters in 3 and 2 mu m CMOS processes reached input frequencies of 400 and 750 MHz, respectively, or nearly 80 and 70% of the intrinsic speeds of these processes. Pipelined accumulators in 2 and 1.2 mu m CMOS processes operated at up to 430 and 700 MHz clock frequencies, respectively. The data rate of an error correcting encoder designed for an optical fiber communication link was measured as 1.2 Gb/s, while the corresponding decoder was simulated at the same speed. In general, the circuits were found to be as robust as CMOS circuits designed in a conventional way.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed CMOS circuit technique

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

Bit-serial realisations of maximum and minimum filters

Efficient bit-serial realisations for maximum and minimum filters are presented. The proposed circuits are simple and suitable for VLSI implementation. The filters not only give the maximum or minimum values, but also indicate which input is the maximum or minimum in an input vector. A true single phase clock has been used to achieve high speed.