True Single Phase Clock Research Articles

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively.

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6dBc/Hz at 1MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1mW. The chip with an area of 1.048×1.076mm2 is fabricated in a TSMC 0.18μm CMOS 1P6M technology process.

Pre‐emphasis transmitter (0.007 mm 2 , 8 Gbit/s, 0–14 dB) with improved data zero‐crossing accuracy in 65 nm CMOS

A pre-emphasis transmitter with improved data zero-crossing accuracy is described. It is achieved via data re-synchronisation using a set of extended true single-phase clock latches before output combining, constituting a robust, area- and power-efficient solution. Fabricated in 65 nm CMOS, the full-rate one-tap pre-emphasis transmitter measures a total jitter of 33.12 ps up to an 8 Gbit/s data rate, and 25.04 to 38.75 ps under a 0–14 dB reconfigurable pre-emphasis range. The achieved output swing is as large as 550 mVpp, and the active area is just 0.007 mm2.

Design of Low Noise 10 GHz divide by 16…511 Frequency Divider

In this paper design and simulation of a 10 GHz, divide‑by‑16…511 programmable frequency divider based on ETSPC and TSPC logic flip-flops in 65 nm CMOS are presented. Main blocks of the divider are three-stage dual modulus divide by 2/3 divider chain, 6-bit counter, jitter removal and synchronisation flip-flops. Extended True Single Phase Clock (ETSPC) logic is used for 2/3 dividers to achieve high input frequency and low power and TSPC logic is used for 6-bit counter. Simulation of the divider was made using Cadence software. Divider’s operation frequency is up to 10 GHz. Resulted phase noise is -143.7 dBc/Hz at 1 kHz offset from output frequency and power dissipation is 29.35 mW when input frequency is 10 GHz, division ratio is set to 23, supply voltage 1.2 V. The main application of such divider is as feedback divider in frequency synthesizer for wireless communication systems.DOI: http://dx.doi.org/10.5755/j01.eee.19.6.4570

Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip–Flops Under the Negative Bias Temperature Instability Effect

With the CMOS transistors being scaled to 28 nm and lower, negative bias temperature instability (NBTI) has become a major concern due to its impact on pMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of CMOS flip-flops. First, it is shown that the NBTI effect tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, an efficient algorithm is introduced for characterizing codependent setup and hold time contours of the flip-flops. Third, a multicorner optimization technique, which relies on mathematical programming to find the best transistor sizes, is presented to minimize the energy-delay product of the flip-flops under the NBTI effect. Finally, the proposed optimization technique is applied to true single-phase clock flip-flops to demonstrate its effectiveness.

Low‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier

In this study, a low-power, high-speed, layout-efficient 8 b × 8 b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 μm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.

DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

This paper enumerates low power, high speed design of flip-flop having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and one transistor clocked, thus has lesser size and lesser power consumption. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The analysis for various flip flops and latches for power dissipation and propagation delays at 0.13μm and 0.35μm technologies is carried out. The leakage power increases as technology is scaled down. The leakage power is reduced by using best technique among all run time techniques viz. MTCMOS. Thereby comparison of different conventional flip-flops, latches and TSPC flip-flop in terms of power consumption, propagation delays and product of power dissipation and propagation delay with SPICE simulation results is presented.

A low-power high-speed true single phase clock divide-by-2/3 prescaler

A low-power high-speed true single phase clock divide-by-2/3 prescaler

Design and Analysis of Low Power CNTFET TSPC D - Flip Flop Based Shift Registers

This paper enumerates the efficient design and analysis of low power CNTFET True single phase clock logic D Flip flop based shift registers. The TSPC D flip flop and shift registers are designed using Stanford University CNTFET model and proposed 10nm CNTFET model with sleepy keeper low power technique. The CNTFET is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage of 1V and the operating frequency at 1GHz. The simulation results are obtained and the analysis are compared with circuits designed using 32nm MOSFET. The comparison results are indicated that the proposed 10nm CNTFET based design and the low power technique are more efficient in power saving as compared to MOSFET design.

A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

A true single-phase clocked flip-flop with leakage current compensation

A true single-phase clocked (TSPC) flip-flop, which compensates for the leakage current generated at dynamic nodes, is proposed to cover a wide operational frequency range in submicron CMOS processes. To implement the proposed TSPC flip-flop, three feedback circuits composed of a gated inverter (GI) are added to the conventional TSPC flip-flop. The GI is controlled by a clock and the internal signal of the conventional flip-flop, without an external control signal or a complementary clock signal. Furthermore, the strength ratio of the normal path to the feedback path does not need to be considered for the proposed TSPC flip-flop since the feedback circuit is only enabled when the dynamic node acquires a floating state. The proposed TSPC flip-flop is designed using a 1-poly 6-metal 65nm CMOS process with a 1V supply voltage. The simulation results show that the proposed TSPC flip-flop, which is optimized for normal operation at an operational frequency of 2GHz, exhibits an error-free operation at low operational frequencies such as 1MHz. The three added feedback circuits increase the power consumption by 8.8% as compared to that of the conventional TSPC flip-flop and occupy 12.28% of the proposed flip-flop.

A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

Lower-power TSPC-based Domino Logic Circuit Design with 2/3 Clock Load

In this paper, we propose a low-power true single-phase-clock (TSPC) based domino logic circuit design. Compared to using three clock transistors in the conventional TSPC-based scheme, the proposed circuit only requires two transistors. As a result, the clock load capacitance is reduced, leading to low power consumption in the clock distribution network. A keeper design to solve charge sharing is also demonstrated. Simulation results using 90nm and 45nm CMOS technologies are provided and iscussed, respectively, which illustrate power saving as compared to conventional design not only when the input logic is active but also when the input logic is held to zero.

Low power consumption high speed CMOS dual-modulus 15/16 prescaler for optical and wireless communications

Frequency synthesizer is an important part of optical and wireless communication system. Low power comsumption prescaler is one of the most critical unit of frequency synthesizer. For the frequency divider, it must be programmable for channel selection in multi-channel communication systems. A dual-modulus prescaler (DMP) is needed to provide variable division ratios. DMP is considered as a critical power dissipative block since it always operates at full speed. This paper introduces a high speed and low power complementary metal oxide semiconductor (CMOS) 15/16 DMP based on true single-phase-clock (TSPC) and transmission gates (TGs) cell. A conventional TSPC is optimized in terms of devices size, and it is resimulated. The TSPC is used in the synchronous and asynchronous counter. TGs are used in the control logic. The DMP circuit is implemented in 0.18 μm CMOS process. The simulation results are provided. The results show wide operating frequency range from 7.143 MHz to 4.76 GHz and it comsumes 3.625 mW under 1.8 V power supply voltage at 4.76 GHz.

A Low Power Multi-Modulus Programmable Divider with TSPC Technology

A lower power multi-modulus programmable divider is designed in this paper. The TSPC (True Single Phase Clock) Technology is used and the TSPC D flip-flop with an AND gate embedded is designed, which significantly lower the power dissipation of the programmable divider. It is designed by Cadence in Chartered 0.18 μm CMOS process, simulated under condition that the supply voltage is 1.8 V, and the frequency of input signal is 1.8 GHz. The simulation result shows that this programmable divider can operate well with achieving multi-modulus frequency dividing from 128 to 254 with step of two. And the whole power dissipation is 3.27 mW from a 1.8 V supply. The designed programmable divider has good stability and low power, and it is easily to expand the range of dividing ratios. It is very suitable for the application of the high stability frequency synthesizer in wireless communication system.

The Speed–Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers

In this work, we introduce a true-single-phase-clock (TSPC) divider synthesis technique that is based on the general TSPC logic family. According to this unified technique, various types of TSPC dividers are compared in terms of the speed-power trade-off. The newly proposed RE-2 type has shown better balance between speed and power performance than other types. The measurement results of a prototype design in a 65 nm LP CMOS technology show that the maximal input frequencies can be 19 GHz and 16 GHz for a divide-by-2 divider and a divide-by-2/3 prescaler respectively, and the power consumption is less than 0.5 mW.

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop (PLL) design for low voltage (0.8 V) applications is presented. The voltage controlled oscillator (VCO) operates from a 0.5 V voltage supply, while the other blocks operate from a 0.8 V supply. A differential NMOS-only topology is adopted for the oscillator, a modified precharge topology is applied in the phase-frequency detector (PFD), and a new feedback structure is utilized in the charge pump (CP) for ultra-low voltage applications. The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power. In addition, several novel design techniques, such as removing the tail current source, are demonstrated to cut down the phase noise. Implemented in the SMIC 0.13 μm RF CMOS process and operated at 0.8 V supply voltage, the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz. The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply. The occupied chip area of the PFD and CP is 100 × 100 μm2. The chip occupies 0.63 mm2, and draws less than 6.54 mW from a 0.8 V supply.

Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a chartered 0.18 ¿m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.

A CMOS True Single-Phase-Clock Divider With Differential Outputs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This letter presents a true single-phase-clock (TSPC) divider that takes a single-ended input signal while producing differential outputs. The differential outputs are generated by properly coupling the waveforms of two TSPC dividers. Implemented using TSMC 0.18 <formula formulatype="inline"> <tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS technology, the divider is capable of operating from 0.6 to 5 GHz. The phase deviation and amplitude difference of the differential outputs are less than 1.7 degree and 0.41%, respectively, below 3 GHz. The core circuit size of the TSPC divider is <formula formulatype="inline"><tex Notation="TeX">$160\ \mu{\rm m}\times 215\ \mu{\rm m}$</tex></formula>. </para>

High-Speed Memory Cell Circuit Design Based on Low-Temperature Poly Silicon TFT Technology

In this paper, low-temperature poly-silicon (LTPS) thin-film transistors (TFT) are used for LTPS memory on glass substrates. System on panel (SOP), combined with memory, controller, and driver circuits on a glass substrate, will be the most suitable applications for TFT panels in the near future. Recently, the low-temperature poly-silicon thin-film transistors prepared on glass substrates have been studied extensively. Compared to amorphous silicon TFT (a-Si TFT), the LTPS TFT has electron mobility that is several orders of magnitude higher. Therefore, it is possible to integrate the LTPS TFT with peripheral circuits on the same glass substrate for advanced flat panel display applications. We use LTPS technology to achieve a high-speed memory cell that adopts a true single phase clocking (TSPC) circuit. Finally, the experimental results show that the high-speed TSPC LTPS-TFT memory operates at 24 MHz and accomplishes the SOP design target.