A Low Power Multi-Modulus Programmable Divider with TSPC Technology

Abstract

A lower power multi-modulus programmable divider is designed in this paper. The TSPC (True Single Phase Clock) Technology is used and the TSPC D flip-flop with an AND gate embedded is designed, which significantly lower the power dissipation of the programmable divider. It is designed by Cadence in Chartered 0.18 μm CMOS process, simulated under condition that the supply voltage is 1.8 V, and the frequency of input signal is 1.8 GHz. The simulation result shows that this programmable divider can operate well with achieving multi-modulus frequency dividing from 128 to 254 with step of two. And the whole power dissipation is 3.27 mW from a 1.8 V supply. The designed programmable divider has good stability and low power, and it is easily to expand the range of dividing ratios. It is very suitable for the application of the high stability frequency synthesizer in wireless communication system.