Triple Modular Redundancy Scheme Research Articles

X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems

Triple modular redundancy (TMR) is one of the most common techniques in fault-tolerant systems, in which the output is determined by a majority voter. However, the design diversity of replicated modules and/or soft errors that are more likely to happen in the nanoscale era may affect the majority voting scheme. Besides, the significant overheads of the TMR scheme may limit its usage in energy consumption and area-constrained critical systems. However, for most inherently error-resilient applications such as image processing and vision deployed in critical systems (such as autonomous vehicles and robotics), achieving a given level of reliability has more priority than precise results. Therefore, these applications can benefit from the approximate computing paradigm to achieve higher energy efficiency and a lower area. This article proposes an energy-efficient approximate reliability (X-Rel) framework to overcome the aforementioned challenges of the TMR systems and get the full potential of approximate computing without sacrificing the desired reliability constraint and output quality. The X-Rel framework relies on relaxing the precision of the voter based on a systematical error bounding method that leverages user-defined quality and reliability constraints. Afterward, the size of the achieved voter is used to approximate the TMR modules such that the overall area and energy consumption are minimized. The effectiveness of employing the proposed X-Rel technique in a TMR structure, for different quality constraints as well as with various reliability bounds, is evaluated in a 15-nm FinFET technology. The results of the X-Rel voter show delay, area, and energy consumption reductions of up to 86%, 87%, and 98%, respectively, when compared to those of the state-of-the-art approximate TMR voters. Also, the effectiveness of the proposed X-Rel-based TMR structure is assessed in four benchmark applications from different domains. For these benchmarks, the results show 1.59 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> , 2.35 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> , and 3.39 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> energy-delay-area-product (EDAP) reduction for less than 1%, 5%, and 10% output quality degradations, respectively. Finally, an image processing application is benchmarked to evaluate the X-Rel framework efficacy in the presence of errors, where the results show up to a 4.78 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> higher output image quality in comparison with the typical TMR voters.

ПОВЫШЕНИЕ ФУНКЦИОНАЛЬНОЙ НАДЕЖНОСТИ СИСТЕМ БИОМЕТРИЧЕСКОЙ ИДЕНТИФИКАЦИИ ПУТЕМ ВНЕСЕНИЯ ИЗБЫТОЧНОСТИ

The paper demonstrates a need to study the functional reliability of identification systems and the applicability of methods for ensuring the functional reliability of information systems for biometric identification systems. Methods of ensuring functional reliability of biometric identification systems via providing indicators of reliability of identification devices and introducing redundancy are considered. The applicability of the methods for biometric identification systems is investigated, its advantages and disadvantages are evaluated. Triple modular redundancy scheme has been developed for the program redundancy using N-version programming. An appropriate reliability scheme based on the principles of dual programming has been developed to implement the identification system with one additional redundant element. Based on the NIST statistics of face recognition algorithms for the developed reliability schemes the reliability indicators were evaluated and its advantages over a system consisting of a single non-redundant element have been shown. The proposed reliability schemes are consistent with the practice of ensuring the functional reliability of information systems and can be integrated into biometric identification systems that use biometric data as the main access identifier.

Reliable speed control of a separately excited DC motor using advanced modified triple modular redundancy scheme in H-bridges

The risk of danger in industries is increasing due to the unexpected shutdowns owing to the unwanted faults in the components. These faults can also lead to a complete failure of the system causing costly production losses and safety issues. Therefore, Fault-Tolerant Control (FTC) techniques are used for such systems to get better reliability, and safety to prevent faults. This paper presents a Modified Triple Modular Redundancy (MTMR) based fault-tolerant system for a separately excited Direct Current (DC) motor with a Fault Detection and Isolation (FDI) unit that can detect, isolate, and replace the faulty switch with the standby switches to prevent the unwanted shut down of the system and support the process continuity thereby increasing reliability. The proposed MTMR will still be able to provide output with only one healthy switch with the other two in the faulty conditions. MATLAB/Simulink software was used for the experimentation process to check the performance of the system. The presented work establishes that the MTMR-based fault-tolerant H-bridge with the FDI unit is a highly reliable solution for the speed control of a separately excited DC motor. The comparison of the proposed work with existing works also demonstrates its superior performance.

A Novel Scheme for Fault Tolerant Computing

A novel scheme for ensuring reliability in the operation of a combinational digital network has been offered in this paper. This has been achieved by making use of three copies of the same digital network along with two additional sub-networks, one of which consists of three additional control inputs, which can also be used as additional observable outputs. If both the said two sub-networks are fault free, then the primary output of the network in the present scheme will always give fault-free responses even if a fault (single or multiple) occurs in one of the three copies of the digital network under consideration. Unlike the Triple Modular Redundancy (TMR) scheme, the present scheme does not require any majority voter circuit. Furthermore, unlike the TMR scheme, the additional sub-networks in the present scheme can be tested off-line by predefined test input patterns.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

Dynamic partial reconfiguration scheme for fault‐tolerant FFT processor based on FPGA

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

On the Structural Robustness Assessment of Wireless Communication Systems for Intra-Satellite Applications

When a system has been designed to be robust against other phenomena different than ionizing radiation, it is possible that the robustness introduced by design in its structure may also make it tolerate some radiation effects. The present work explores how to exploit the self-correcting features that transmitter-receiver systems have for correcting channel-induced errors, in order to optimally design a radiation-tolerant wireless communications system for intra-satellite communication. A wireless transceiver is a good example of how to proceed to design a system that has some inherent robustness by itself, so fewer protections are needed when hardening it against radiation. The assessment is made using a fault injection technique, where the figure assessed is the transmission Frame Error Rate (FER) instead of the typical cycle-by-cycle comparison with a theoretical, or golden, bit sequence. This assessment allows the designer to optimally protect the transceiver, reducing mitigation area overhead with respect to full and selective Triple Modular Redundancy (TMR) schemas. The technique has been applied to the design of a wireless transmitter, reducing the area overhead required to harden it against Single Event Upsets (SEU), compared with traditional full and selective TMR schemes.

Design and implementation of the highly-reliable, low-cost housekeeping system in the ZDPS-1A pico-satellite

The ZDPS-1A pico-satellite designed in Zhejiang University with a mass of 3.5 kg and a power consumption of less than 3.5 W is the smallest satellite in China up to now. The housekeeping system (HKS) is the core part of ZDPS-1A. The reliability of HKS has an important influence on the safety of the satellite. Traditional fault-tolerant methods do not apply to ZDPS-1A due to such pico-satellite characteristics as light weight, compactness in size, energy saving, and high integration. This paper deals with a highly-reliable, low-cost design for HKS using industrial devices. The reliable strategies of HKS include a dual modular redundancy scheme, CPU warm backup, a static triple modular redundancy scheme, and two-level watchdogs. Recursive experiments, special tests, and environmental tests show that this system meets the design target. This design has already been applied to ZDPS-1A, which was launched to execute in-orbit tasks on Sept. 22, 2010. To date, the satellite has been in a proper state for more than 15 months.

Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic

Dynamically self-checked or fault-tolerant realizations of switching functions and sequential machines are proposed under a fault model that permits arbitrary logic faults in a single-logic module, where the modules are explicitly defined. These realizations permit considerable logic sharing, organized around an (n, m, r)-basis for decomposing switching functions. The logic sharing permits more economical realizations than can be obtained using classical parity and triple-modular redundancy schemes for obtaining logic circuits with the corresponding property.