Triple Metal Gate Research Articles

Nanoscale Trench Gate Engineered JAM Gate-All-Around (TGE-JAM-GAA) Label-Free BioFET for Charged/Neutral Biomolecules Detection

In this manuscript, a Trench Gate Engineered Junctionless Accumulation Mode Gate-All-Around (TGE-JAM-GAA) BioFET structure has been proposed and critically analyzed for the label-free identification of biomolecules using extensive numerical device simulations. This device is superior in terms of a variety of performance metrics, including higher sensitivity, a larger shift in threshold voltage, drain current, transconductance, and the ION/IOFF current ratio. These improvements are due to both the triple metal gate engineering and the trench gate. A comparative analysis of TGE-JAM-GAA BioFET has been performed with a triple metal normal gate JAM Gate-All-Around FET (TMNG-JAM-GAAFET) and a conventional single metal normal gate JAM Gate-All-Around FET (SMNG-JAM-GAAFET) biosensor. For instance, in the case of APTES biomolecules, the drift in threshold voltage obtained is 236.24 mV, which is 58.75% and 159.18% higher than that of the TMNG-JAM-GAAFET and SMNG-JAM-GAAFET, respectively, demonstrating that the TGE-JAM-GAA BioFET is more suitable for applications in biosensing.

Sensitivity enhancement using triple metal gate work function engineering of junctionless cylindrical gate all around SiNW MOSFET based biosensor for neutral biomolecule species detection for upcoming sub 14 nm technology node

In the present work Dielectric Modulation (DM) technique along with Triple Metal (TM) gate engineering has been used for the junctionless (JL) cylindrical gate all around (CGAA) Si nanowire (NW) MOSFET based biosensor for label free electrical detection of neutral biomolecules species like Uricase, Streptavidin, Protein, Biotin, ChOx (choline oxidase), and APTES etc. For this device, the Drift Diffusion approach has been used along with self-consistent solution of Schrodinger’s equation with Poisson’s equation. For the biomolecule immobilization, a nanogap cavity region is formed in the JL SiNW MOSFET by etching gate oxide layer above the SiO2 interfacial layer. The change in the drain current (ID), threshold voltage (Vth), off-current sensitivity (SIoff), threshold voltage sensitivity (SVth) and Ion/Ioff current ratio of the device have been considered as the sensing parameters for detection of biomolecules under dry environment condition. In present work a new sensing metric of sensing of biomolecules – DIBL has been added which has never been reported in literature. In this work for JL SiNW, sensitivity metrics like smaller DIBL ∼50.47 mV/V, higher SIoff9.33×105, higher SVth28.72, nearly ideal subthreshold slope (SS) ∼60 mV/dec, and higher Ion/Ioff current ratio ∼9.01 × 1012 have been obtained in comparison to available literature results.

Assessing the Impact of Source Pocket Length Variation to Examine DC/RF to Linearity Performance of DG-TFET

This research examines the variation in source pocket length at the corner region of source–channel interface (SCi) with hetero-oxide triple metal gate. The investigated DC and analog parameters include energy band profile in ON/OFF state, electric field ([Formula: see text]), potential, transconductance ([Formula: see text]), capacitance gate to source and gate to drain ([Formula: see text], [Formula: see text]), cut-off frequency ([Formula: see text]), gain bandwidth product, transconductance generation factor, transconductance frequency product, transit time ([Formula: see text]) and for linearity figure of merit it includes [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], 1-dB compression point. The comprehensive study is done with varying lengths of source pocket, and while keeping doping of source pocket same and keeping work function of triple metal gate constant, it shows the enhancement in overall device performance triple metal gate hetero-oxide corner source pocket double gate TFET (TMG-HO-CSP-DGTFET).

Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study

This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel and the narrow bandgap source. It shows an Ion of 392 μA/μm, an Ioff of 8.8 × 10−17 A/μm, an Ion/Ioff ratio of about 4.4 × 1012, and a minimum subthreshold slope of 9.3 mV/dec at Vd = 1 V. We also analyze the influence of the gate oxide and metal work functions on the transistor characteristics. A numerical device simulator, calibrated to the experimental data of a vertical InAs–Si gate all around TFET, is used to accurately predict different features of the device. Our simulations demonstrate that the proposed vertical TFET, as a fast-switching and very low power device, is a promising transistor for digital applications.

Performance Investigation of a Dielectric Stacked Triple Material Cylindrical Gate All Around MOSFET (DSTMCGAA) for Low Power Applications

This paper presents an analysis of gate stacked triple material dual-halo cylindrical MOSFET. The surface potential and electric field have been plotted for the proposed device using TCAD Silvaco at various channel lengths. The analytical model of surface potential, field and subthreshold current is also present. A comparative analysis has been accomplished for the proposed device with Asymmetric gate stack triple metal gate all around (AGSTMGAA), dual dielectric triple metal surrounding gate (DDTMSG) and Triple metal surrounding gate MOSFET. The performance metric of the device has been investigated in terms of Drain Induced Barrier Lowering (DIBL), Subthreshold swing and threshold-voltage roll-off. Furthermore, the analog behaviour of the device has been evaluated by determining transconductance, early voltage and intrinsic gain. The proposed device shows much better performance when compared to its counterpart. The mitigation in DIBL and leakage current indicates the cut back in the SCEs. The proposed device shows 8% improvement in SS, 36.2% improvement in DIBL and 13.5% improvement in threshold voltage roll-off as compared to AGSTMGAA. Hence, it can be used for low power applications.

Design and investigation of triple metal gate engineering of charge plasma based TFET for biomolecule detection

The current manuscript introduces a dielectric regulated charge plasma based Triple metal Gate Tunnel Field Effect Transistor (CPB-TG-TFET) biological sensor. In which a nano-cavity is introduced below the gate and source electrode to detect the biological molecules like amino acids (AAs), protein, etc. The proposed P + and N + regions are contrived depending upon the electrode’s work function on the device’s silicon body. The effects of metal electrode work function modulation, gate electrode length variation and gate oxide thickness variation are analyzed for improving band-to-band tunneling efficiency at the source- channel transition. The proposed structure shows noticeable sensitivity results for neutral and charged biomolecules. The sensitivity of the neutral biomolecules having higher dielectric constant(Kp) is observed higher; the surface potential sensitivity of the Gelatin (Kp = 14) is estimated as 3.×1010 which is 13% and 35% higher than the sensitivity of Keratin (Kp = 10) and Bacteriophage T7 (Kp = 5) respectively at the cavity length of 30 nm.

Subthreshold Analytical Model of Asymmetric Gate Stack Triple Metal Gate all Around MOSFET (AGSTMGAAFET) for Improved Analog Applications

In this paper, we have proposed a 2D analytical model for Asymmetric gate stack triple metal gate MOSFET(AGSTMGAAFET) and performed a comparative analysis with the simulation results obtained using the SILVACO 3D simulation software. Existing devices such as gate all around single metal (SMGAAFET), gate all around triple metal (TMGAAFET), gate stack single metal (GSSMGAAFET), gate stack triple metal (GSTMGAAFET) and asymmetric gate stack single metal (AGSTMGAAFET) have been compared with our proposed structure AGSTMGAAFET. Our device provides excellent performance in terms of drain current, transconductance, output conductance, current gain, maximum transducer power gain which shows our device’s suitability for various analog applications moreover the potential and electric field plots obtained have twostep profile and extremely low electric field near the drain region which ordains our device with the ability to suppress various SCE’s like DIBL and hot-carrier effect. The analytical model and simulation results show good convergence in values which validate the correctness of the proposed model.

Analytical modeling of transport phenomena in heterojunction triple metal gate all around tunneling field effect transistor

An analytical model for the transport phenomena of a heterojunction triple metal gate all around tunneling field effect transistor (HTM GAA TFET) is developed for the first time in this paper. The continuous surface potential profile of the staggered-gap aligned heterojunction device is achieved by solving Poisson’s equation, and then, Kane’s model for band to band tunneling is used to derive the drain current of the device. The comparison between the modeling results and Technology Computer Aided Design (TCAD) simulation results with the GaAs0.5Sb0.5/In0.53Ga0.47As heterojunction stems satisfactory consistency. The robust and compatible model approaches the surface potential, electric field, band to band tunneling generation rate, and drain current in an HTM GAA TFET in a methodical manner. The influences of gate oxide thickness, gate oxide dielectric constant, and gate metal work functions on the performance of the considered device are also investigated. To achieve an impactful perspective, the subthreshold swing, Ion/Ioff ratio, and threshold voltage of the device are reviewed as well.

Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D SOI MOSFET has the capability to reduce the series resistance of the device due to the extended depth of source and drain into buried oxide layer. So the current drive capability of this device is improved which in turn improves the input/output switching in the inverter and ring oscillator. In this paper, transfer characteristics, delay and frequency is analyzed for inverter as well as for ring oscillator with TMG Re-S/D SOI MOSFET. DC and transient analysis such as transfer characteristics, noise margin, power dissipation, delay, and frequency is done for CMOS inverter and ring oscillator. Also, the Voltage Transfer Characteristic (VTC) has been compared with the available SMG and DMG structures of Re-S/D FD SOI MOSFET for the analysis switching behavior. This DC and transient simulation are performed using 2-dimensional numerical TCAD simulator ATLAS from Silvaco.

Perspective of Buried Oxide Thickness Variation on Triple Metal-Gate (TMG) Recessed-S/D FD-SOI MOSFET

Recently, Fully-Depleted Silicon on Insulator (FD-SOI) MOSFETs have been accepted as a favourable technology beyond nanometer nodes, and the technique of Recessed-Source/Drain (Re-S/D) has made it more immune in regards of various performance factors. However, the proper selection of Buried-Oxide (BOX) thickness is one of the major challenges in the design of FD-SOI based MOS devices in order to suppress the drain electric penetrations across the BOX interface efficiently. In this work, the effect of BOX thickness on the performance of TMG Re-S/D FD-SOI MOSFET has been presented at 60 nm gate length. The perspective of BOX thickness variation has been analysed on the basis of its surface potential profile and the extraction of the threshold voltage by performing two-dimensional numerical simulations. Moreover, to verify the short channel immunity, the impact of gate length scaling has also been discussed. It is found that the device attains two step-up potential profile with suppressed short channel effects. The outcomes reveal that the Drain Induced Barrier Lowering (DIBL) values are lower among conventional SOI MOSFETs. The device has been designed and simulated by using 2D numerical ATLAS Silvaco TCAD simulator.

A Comparative Numerical Study of Junctionless and p-i-n Tunneling Carbon Nanotube Field Effect Transistor

In this paper, a gate-all-around junctionless tunnel field effect transistor (JL-TFET) based on carbon nanotube (CNT) material is introduced and simulated. The JL-TFET is a CNT-channel heavily n-type-doped junctionless field effect transistor (JLFET) which utilizes two insulated gates (Control-Gate, P-Gate) with two different metal workfunctions in order to treat like tunnel field effect transistor (TFET). In this design, the privileges of JLTFET and TFET are mixed together. The numerical comparative study on the performance characteristics of JL-TFET and conventional p-i-n TFET demonstrated that the proposed JL-TFET has a higher ON-state current driveability (ION), a larger ON/OFF-current ratio (ION/IOFF), a lower drain induced barrier lowering (DIBL), a shorter delay time (τ), and also a superior cut-off frequency (ƒT). Moreover, in order to further performance improvement of proposed JLTFET, three novel device structures namely as junctionless linear descending gate workfunction TFET (JL-LDWTFET), junctionless linear ascending gate workfunction TFET (JL-LAWTFET) and junctionless triple metal gate TFET (JL-TMGTFET) are proposed by gate workfunction engineering approach. According to simulation results, the JL-TMGTFET with the gate composed of three segments of different work functions shows excellent characteristics with high ION/IOFF ratio, a superior ambipolar characteristic, a shorter delay time and a better cut-off frequency compared to conventional p-i-n TFET and other proposed junctionless-based features. All the simulations are done with the full quantum mechanical simulator for a channel length of 60-nm using nonequilibrium Green’s function (NEGF) method.

Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers

The effect of a triple metal-gate (TMG) on the performance and on the ambipolar current in a TMG vertical tunnel field-effect transistor with triple metal-gate (TMG-TFET) is investigated using technology computer-aided design simulation. The TMG-TFET is designed to tackle the performance as well as the ambipolar current, simultaneously, by modulating the TMG parameters—the work function of the TMG and/or the length of each MG—that have critical impacts on the energy-band diagrams of the channel region. The tempered on-/off-current ratio of $10^{\mathrm { {8}}}$ and the steep average subthreshold slope of 43.5 mV/decade at a power supply voltage of 0.5 V are ascribed to the formation of an energy barrier in the channel by the optimal device parameters. It is found that two main flaws in a conventional (single-material gate) TFET, which are the degraded on-state current and the ambipolar current, can be successfully controlled by adjusting the TMG structure.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Analog and RF Performance Analysis of a Junctionless Electrically Induced Source/Drain Extension Cylindrical Surround Gate (JLEJ-CSG) MOSFET

Junctionless (JL) transistors have recently been reported as strong candidate for the future technology nodes because of ease of manufacturing and improved performance over conventional MOSFETs. In this paper, the analog and RF performances of a JL transistor have been evaluated with metal gate structure having higher work function in the middle with two side gates of lower work function (electrically induced source/drain junctions, EJ). This triple metal gate JLEJ cylindrical surrounding gate (CSG) MOSFET provides better response in terms of intrinsic gain, transconductance generation factor, early voltage, unity gain transition frequency, maximum frequency of oscillation, etc. over single metal junctionless cylindrical surrounding gate (JLSM) transistors. However, the analog and RF performance metrics have been observed to be degraded because of quantum mechanical effects. The ION/IOFF ratio is improved by more than 105 times.