Trigger Current Research Articles

Preparation and Application of Novel Power Semiconductor Chips

This study aims to improve the triggering current and dynamic characteristics of thyristor chips by designing new gate structures and multilayer semiconductor structures. Thyristor chips are essential components in power electronic devices, widely used in fields such as power transmission, motor control, and energy conversion systems. Trigger current is a key factor in the performance of thyristor chips, which is responsible for initiating the conduction state of the thyristor and carrying high current under high voltage conditions. This study improved the triggering current and dynamic characteristics of thyristor chips by optimizing the chip structure, especially by introducing multilayer P/N semiconductor design and improving the gate structure. The research results provide important guidance for the future development of thyristor chips and also contribute to the advancement of semiconductor technology.

Reduction of the welding fume emission rate of gas-shielded cored wires by the MAG pulse welding process variant

The aim of the study is to reduce welding fume emissions from flux-cored wires using pulse technology. Low-alloyed cored wires of the rutile, basic, and metal powder types were selected for this purpose. The analyses were carried out on a DIN EN ISO 15011–1:2010 compliant test rig. In addition, high-speed recordings of the material transition mode and metallographic cross-sections were made to interpret the results. Using characteristic curves developed in pre-tests, the influence of pulse time, pulse frequency, and trigger current on the welding fume emission potential of the rutile cored wire was first determined. Short pulses, medium trigger current, and medium pulse frequency were found to have a positive influence on the emission rate.Finally, the welding fume emissions of the conventional characteristic are compared with the emission-optimized pulse characteristic. For all three filling types, emission reductions of up to 41% were found when using the pulse technology. When considering the ratio of fume generated to the mass of the weld metal produced, with the associated greatly reduced economy of the process, it became apparent that pulse welding is not suitable for welding cored wires without restrictions.In summary, the suitability of pulse GMAW technology for reducing welding fume emissions can also be confirmed for flux-cored wires.

Investigation on Triggering Mode and Criterion of 4H-SiC Diode Avalanche Shaper

In this article, the requirements of voltage rise rate for punched-through (PT) structure diode avalanche shaper (DAS) triggering and the current conditions for PT and non-punchthrough (NPT) structures’ DAS triggering are given. The triggering mode of DAS is studied through experiment and simulation, and it is divided into four types: non-trigger; early trigger; half trigger; and full trigger. DAS has the fastest opening speed and the lowest residual voltage under full trigger mode; DAS is most susceptible to failure when operating in early trigger mode with the highest temperature rise. In the end, based on the current conditions proposed in this article, the criterion methods of four triggering modes are given and the differences in triggering conditions between the 4H-silicon carbide (SiC) DAS and Si DAS are compared with the help of it. The results show that 4H-SiC DAS is less likely to early trigger and has lower requirements for the rising rate of the trigger current.

Research on the Operating Characteristics of Electrically Triggered Vacuum Surface Flashover Switch

A novel configuration of electrically triggered vacuum surface flashover switch (VSFS) is introduced, and switches based on alumina, quartz, and aluminum nitride are fabricated. The main switch operation characteristics (flashover voltage, turn-on time, delay time, jitter, repetitive frequency ability, and lifetime) and their influencing factors (operation voltage, loop current, trigger current, and trigger waveform) are experimentally investigated. The results show that the dc flashover voltages for both switches tested in vacuum are 2–4 times higher than the voltages tested at 1 atm. The switch turn-on time is mostly affected by the operation voltage and loop resistance, while the switch delay time is mainly influenced by the front edge of the trigger voltage pulse. Delay times of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 70$ </tex-math></inline-formula> ns with a corresponding jitter of less than 3.1 ns are observed for both switches. The repetitive frequency ability of both switches is better than 60 Hz@27.5 kV and can reach 100 kHz@6 kV. The delay time, turn-on time, and jitter of alumina switch remained unchanged during <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 105~000$ </tex-math></inline-formula> triggered discharges (@27.5 kV, 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load, 60 Hz). The optimum operating mode of the switch is determined from the experimental results.

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed.

Influence of Trigger Pulse on the Trigger Characteristics of Surface Flashover Trigger Vacuum Switch

Surface flashover triggered vacuum switch (STVS) working performance mainly depends on the electrical characteristics of trigger pulse. This article presents an experimental investigation of the trigger process. The influence of the electrical properties of the trigger pulse on the trigger characteristics is focused. Based on the self-developed high-performance STVS product, the experimental test platform was established. The experimental results show that a shorter delay time of STVS can be obtained by heightening trigger voltage. However, the effect of trigger voltage on time jitter is not obvious. The slight increase in trigger current has evident influence on trigger delay time. It also does not affect the stability of trigger delay. With the increase in trigger voltage rise rate, the trigger delay time and time jitter can be optimized. Finally, the long-term stability of STVS is discussed. After 300 trigger times, the delay time changes from about 140 ns to more than 150 ns and the jitter changes from about 5 ns to more than 10 ns. In the design of STVS products, it is recommended to adopt a trigger system with a fast rise rate of trigger voltage and trigger current.

Low-Voltage Triggered VO2 Hybrid Metasurface Used for Amplitude Modulation of Terahertz Orthogonal Modes

Actively tuning of terahertz (THz) waves through hybrid metasurface has important applications in THz communication, imaging, and modulation. In this paper, we propose a vanadium dioxide (VO2) hybrid metasurface to realize amplitude modulation of THz orthogonal modes at low triggering voltage. The unit cell of the hybrid metasurface consists of two identical gold crosses and a central bar. And two rectangular VO2 patterns are symmetrically embedded in the gaps of the crosses. The performance of the hybrid metasurface is simulated and optimized by using full wave electromagnetic calculation software. The sample is fabricated using a surface micromachining process and characterized by a THz time-domain-spectroscopy (TDS) system. The experimental results show that, the amplitude modulation depth reaches 68% in the range of 0.1~0.8 THz for transverse-magnetic (TM) mode. Moreover, the hybrid metasurface changes from the transparency to the stopband near 0.43 THz for transverse-electrical (TE) mode. A switching time of 1.9 s is achieved when the triggering current is 520 mA and the voltage is 3.65 V. Most importantly, a fast response area is found. If the metasurface is biased with a current of 430 mA near the fast response area, it's easy to switch quickly. This work paves a new way for the miniaturization and integration of electronic-controlled THz switches and modulators.

Laser Illumination Adjustments for Signal-to-Noise Ratio and Spatial Resolution Enhancement in Static 2D Chemical Images of NbOx/IGZO/ITO/Glass Light-Addressable Potentiometric Sensors

In a previous study, a thin In-Ga-Zn-oxide light addressable potentiometric sensor (IGZO LAPS) was indicated to have the advantages of low interference from ambient light, a high photocurrent and transfer efficiency, and a low cost. However, illumination optimization to obtain two-dimensional (2D) chemical images with better spatial resolutions has not been fully investigated. The trigger current and AC-modulated frequency of a 405-nm laser used to illuminate the fabricated IGZO LAPS were modified to check the photocurrent of the sensing area and SU8–2005 masking area, obtaining spatial resolution-related functions for the first time. The trigger current of illumination was adjusted from 0.020 to 0.030 A to compromise between an acceptable photocurrent and the integrity of the SU8–2005 masking layer. The photocurrent (PC) and differential photocurrent (DPC) versus scanning length (SL) controlled by an X-Y stage were used to check the resolved critical dimensions (CDs). The difference between resolved CD and optically measured CD (e.g., delta CD) measured at an AC frequency of 500 Hz revealed overall smaller values, supporting precise measurement in 2D imaging. The signal-to-noise ratio (SNR) has an optimized range of 2.0 to 2.15 for a better resolution for step spacings of both 10 and 2 μm in the scanning procedure to construct static 2D images. Under illumination conditions with a trigger current of 0.025 A and at an AC frequency of 500 Hz, the spatial resolution can be reduced to 10 μm from the pattern width of 6 μm. This developed methodology provides a quantitative evaluation with further optimization in spatial resolution without an extra cost for applications requiring a high spatial resolution, such as single-cell activity.

Design, Simulation and Experimental Verification of Chip-Level Cracking Structure

To quickly destroy chip and ensure information security, the author designed a cracking structure of transient-failure integrated circuit in this paper. By placing the Ni-Cr film resistance and the energetic material between the chip and the package and heating the resistance by an electric current, the energetic material expanded and the chip cracked. The information on the chip was destroyed, destroying the information on the chip. The author simulated the temperature distribution and stress of the power-on structure in different sizes by ANSYS software. The simulation results indicate that, the chip cracks within 50ms under the trigger current of 0.5A when a circular groove with an area of 1mm2 and depth of 0.1mm is filled with an expansion material with an expansion coefficient of 10- 5·℃-1. Then the author prepared a sample for experimental verification. Experimental results show that the sample chip quickly cracks and fails within 10ms under the trigger current of 1A. The simulation and experimental results confirm the feasibility of the structure in quick destruction, which lays the foundation for developing instantaneous-failure integrated circuit products to meet information security applications.

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific on-resistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

Design, Simulation, and Experimental Verification of a Destruction Mechanism of Transient Electronic Devices

To quickly destroy electronic devices and ensure information security, a destruction mechanism of transient electronic devices was designed in this paper. By placing the Ni-Cr film resistance and the energetic material between the chip and the package and heating the resistance by an electric current, the energetic material expanded and the chip cracked. The information on the chip was destroyed. The author simulated the temperature distribution and stress of the power-on structure in different sizes by ANSYS software. The simulation results indicate that the chip cracks within 50 ms under the trigger current of 0.5 A when a circular groove with an area of 1 mm2 and depth of 0.1 mm is filled with an expansion material with an expansion coefficient of 10−5°C−1. Then, the author prepared a sample for experimental verification. Experimental results show that the sample chip quickly cracks and fails within 10 ms under the trigger current of 1 A. The simulation and experimental results confirm the feasibility of the structure in quick destruction, which lays the foundation for developing instantaneous-failure integrated circuit products to meet information security applications.

ПРИМЕНЕНИЕ САМОВОССТАНАВЛИВАЮЩИХСЯ ПРЕДОХРАНИТЕЛЕЙ «POLYSWITCH» ДЛЯ ПРЕДОТВРАЩЕНИЯ ТОКОВЫХ ПЕРЕГРУЗОК В ФОТО-ЭЛЕКТРИЧЕСКИХ СИСТЕМАХ

Актуальность. Имеющиеся на настоящий момент результаты моделирования и экспериментальные данные свидетельствуют, что обводные диоды в подпанельных строках фотоэлектрических элементов не полностью защищают от появления «горячих пятен». Обводные диоды более эффективны для предотвращения «горячих пятен» при очень коротких длинах строк ФЭП, что не применяется в современной конструкции панелей из экономических соображений. Поэтому необходимо повышения надежности солнечных батарей, включая устранение нештатных (пожароопасных) ситуаций на основе разработки методов и средств предотвращения токовых перегрузок в их фотоэлектрических системах на основе новых подходов.&#x0D; Цель. Разработка универсального подхода для минимизации токовых перегрузок в фотоэлектрических системах солнечных батарей путем применения недорогостоящих элементов функциональной электроники, в частности, относительно новых и, получивших широкое распространение, самовосстанавливающихся предохранителей типа “Polyswith”.&#x0D; Метод. Предложено схемное решение и методом моделирования обоснованы возможности использования предохранителей типа Polyswitch для предотвращения и минимизации токовых перегрузок в фотоэлектрических системах солнечных батарей. &#x0D; Результаты. Проанализировано влияние величины сопротивления в проводящем состоянии и тока срабатывания предохранителей на вольт-амперные и вольт-ваттные характеристики параллельных соединений фотоэлектрических преобразователей и их модулей.&#x0D; Разработана математическая модель схемного решения и проведено моделирование его основных характеристик при использовании типичных параметров фотоэлектрических преобразователей на основе монокристаллического кремния и коммерческих самовосстанавливающихся предохранителей. Проанализировано влияние величины сопротивления в проводящем состоянии и тока срабатывания СВП на ВАХ и ВВХ параллельного соединения фотоэлектрических компонентов солнечных батарей.&#x0D; Выводы. Показано, что эффективное ограничение тока при наличии короткого замыкания при таком соединении фотоэлектрических компонент может быть реализовано при выполнении следующих условий:&#x0D; – сопротивление предохранителя в проводящем состоянии значительно меньше параллельного соединения последовательных сопротивлений фотоэлектрических компонент;&#x0D; – ток срабатывания предохранителя должен быть больше тока короткого замыкания отдельного фотоэлектрического компонента и меньше тока их параллельного соединения. Библ. 26, рис. 5, табл. 1.

High Trigger Current NPN Transistor With Excellent Double-Snapback Performance for High-Voltage Output ESD Protection

A novel high trigger current NPN transistor (HTC-NPN) with excellent double-snapback performance is developed in $0.5\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. A new floating N+ (FN) layer fabricated in drift-region not only induces two-stage snapback, but also achieves high trigger current ( ${I}_{\text {tr}}$ ) to provide ESD protection for high-voltage (HV) output port without being accidentally triggered on and latch-up like. The operational mechanism and the applied range of the HTC-NPN are discussed in detail, and the double-snapback process induced by the FN is explained via T-CAD simulation as well. From transmission line pulse (TLP) tested results, the proposed HTC-NPN achieved high ${I}_{\text {tr}}$ up to 1.5 A and controllable double-snapback characteristic, thus matching load line from HV output circuit well.

Modeling the Displacement Damage on Trigger Current of Anode-Short MOS-Controlled Thyristor

The MOS-controlled Thyristor (MCT) has been characterized by MOS-gating, high current rise rate, and high blocking capability. The anode short MCT (AS-MCT) is distinguished from conventional MCT by an anode-short structure, which develops a normally-off characteristic. As a composite structure made of metal-oxide-silicon and bipolar junction transistors, AS-MCT is susceptible to displacement damage induced by energetic radiation. The anode trigger current which denotes the latch-up of internal thyristor structure is a key parameter for AS-MCTs. From the aspects of devices physics, we propose a model to describe the displacement damage on trigger current. Our model provides an excellent fit to the experimental data of the AS-MCT samples subjected to fission neutrons with flux in the range of $3.1\times 10^{9}-5.5\times 10^{13}\,\,\mathrm {cm}^{-2}$ . Moreover, this work shows that the high injection effect can alleviate the displacement damage of trigger current following high flux exposures.

Dynamic Voltage Overshoot During Triggering of an SCR-Type ESD Protection

During triggering of an on-board ESD protection, e.g., an SCR, its voltage may temporarily rise to a large value. This work identifies and distinguishes the two major factors that contribute to this voltage overshoot: (1) the conductivity modulation in the silicon and (2) the inductance of the metal traces. The overshoot is shown to have a major impact on the residual current into the IC during a system level discharge (ESD gun test), in particular in high-speed interfaces, such as USB3. This work presents a physics-based behavioral model which accurately describes both contributions to the voltage overshoot. The conductivity modulation model is based on the premise that the doping concentration of a region in the SCR is insufficient to conduct the trigger current. It follows that a minimum charge must be injected into the low-doped region to enable conduction of the trigger current. SCR triggering is delayed until this minimum charge has been injected. During the delay time, the SCR voltage is determined by the high ( $\sim 1~\text{k}\Omega $ ) off-resistance of the device. After triggering, the voltage is determined by the low-impedance ( $\sim 0.25~\Omega $ ) on-resistance. The net effect is a voltage overshoot. This first overshoot is followed by a second inductive voltage overshoot at the time when L.dI/dt is maximum. The paper demonstrates how the resulting model can be used to improve system level robustness for a typical USB3 interface.

Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input–output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET’s to the power rails ( ${V}_{\textsf {DD}}$ or ${V}_{\textsf {SS}}$ ). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells.

Analysis of the Conduction Process for Active Surge Protection Gap With Combination Wave Energy Injection

In this paper, we designed an active coupling trigger circuit and an active surge protection gap (ASPG). The surge protection level of the passive SPG is improved, and the operating time of the passive SPG is shortened. The equivalent circuits for the coupling trigger circuit were developed. Then, we analyzed the component transient voltage of the active coupling trigger circuit with the combination wave injected. We obtained the numerical relationship between the coupling trigger current and the current flowing through the ASPG. In addition, the timing relationship between the component voltage and the current was acquired. To verify the analysis results, we established the combination wave generator and conducted an experiment. In the experiment, we observed that the trigger circuit operating time and the ASPG impulse breakdown voltage changed with the capacitor charging voltage of the combination wave generator. Furthermore, we discovered the change laws. The results also show that the operating time and impulse breakdown voltage of the ASPG are both smaller than the passive SPG. These results provide an important theoretical and experimental basis for the further study and structural optimization of the ASPG.

Chaotization of Oscillations in a Single-Frequency Millimeter-Band Impact Avalanche and Transit-Time Diode Oscillator under the Influence of a Low-Frequency Harmonic Oscillation

The change in the oscillation spectrum of an oscillator based on an impact avalanche and transit-time (IMPATT) diode of the 7-mm range under the action of a low-frequency harmonic oscillation (3 MHz) in the supply circuit of the diode is studied experimentally. It is demonstrated that, if the low-frequency oscillation amplitude exceeds the trigger negative voltage and the working point in the diode volt–ampere characteristic is located either near the trigger current (trigger negative voltage) or far from it, pulsed oscillation mode is established and, consequently, oscillations are chaotized.

A 7.8 kV nanosecond pulse generator with a 500 Hz repetition rate

Pseudospark switches are widely used in pulsed power applications. In this paper, we present the design and performance of a 500 Hz repetition rate high-voltage pulse generator to drive TDI-series pseudospark switches. A high-voltage pulse is produced by discharging an 8 μF capacitor through a primary windings of a setup isolation transformer using a single metal-oxide-semiconductor field-effect transistor (MOSFET) as a control switch. In addition, a self-break spark gap is used to steepen the pulse front. The pulse generator can deliver a high-voltage pulse with a peak trigger voltage of 7.8 kV, a peak trigger current of 63 A, a full width at half maximum (FWHM) of ∼30 ns, and a rise time of 5 ns to the trigger pin of the pseudospark switch. During burst mode operation, the generator achieved up to a 500 Hz repetition rate. Meanwhile, we also provide an AC heater power circuit for heating a H2 reservoir. This pulse generator can be used in circuits with TDI-series pseudospark switches with either a grounded cathode or with a cathode electrically floating operation. The details of the circuits and their implementation are described in the paper.

A high voltage pulse generator based on silicon-controlled rectifier for field-reversed configuration experiment.

A high voltage pulse generator based on a silicon-controlled rectifier has been designed and implemented for a field reversed configuration experiment. A critical damping circuit is used in the generator to produce the desired pulse waveform. Depending on the load, the rise time of the output trigger signal can be less than 1 μs, and the peak amplitudes of trigger voltage and current are up to 8 kV and 85 A in a single output. The output voltage can be easily adjusted by changing the voltage on a capacitor of the generator. In addition, the generator integrates an electrically floating heater circuit so it is capable of triggering either pseudosparks (TDI-type hydrogen thyratron) or ignitrons. Details of the circuits and their implementation are described in the paper. The trigger generator has successfully controlled the discharging sequence of the pulsed power supply for a field reversed configuration experiment.