Tri-gate Nanowire Research Articles

Effects of Side Surface Roughness on Carrier Mobility in Tri-Gate Single Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, the effects of side surface roughness on mobility behaviors in single-silicon-nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) are discussed on the basis of intrinsic carrier mobility data obtained by direct split capacitance–voltage (C–V) method measurement for the first time. To investigate the mechanisms that dominate the mobility degradation in narrower nanowires, low-temperature measurements are performed. It is found that phonon scattering has little dependence on nanowire width, indicating that the mobility degradation in our tri-gate nanowire MOSFETs is caused by surface roughness scattering. It is also found by analyzing the nanowire width dependence of mobility that the process-induced roughness on the side surface is the main source of mobility degradation in nanowire pFETs, while the degradation caused by the side surface roughness is negligible in nanowire nFETs.

Electron mobility in heavily doped junctionless nanowire SOI MOSFETs

• Mobility in highly doped junctionless trigate MOSFETs is experimentally studied. • Mobility enhancement in narrow nanowire versus wide devices is demonstrated. • Mobility values in narrow nanowire MOSFETs exceed the bulk mobility value. • These effects are due to reduced impurity scattering in narrow nanowire devices. This paper presents experimental results on the effective electron mobility in heavily doped tri-gate nanowire junctionless SOI MOSFETs with various nanowire widths. Significant enhancement of the electron mobility in narrow nanowire devices, as compared to counterpart planar (wide) devices, having the same film thickness and doping, and as compared to the bulk silicon mobility with the same doping is demonstrated. This effect is attributed to the reduced impurity scattering in narrow nanowire devices. The obtained results are seen to be very important as low carrier mobility due to high doping was previously assumed to be the fundamental limitation of junctionless nanowire devices.

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

We report an experimental study of the carrier transport in [110]-oriented long channel tri-gate (TG) and omega-gate (ΩG) silicon nanowire (SiNW) transistors cross-section down to 11nm×10nm. Electron and hole mobilities have been measured down to 20K to evaluate the contribution from the dominant scattering mechanisms. We have studied and discussed the influence of channel shape, channel width and strain effect on carrier mobility. In particular, we have shown that the transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and ΩGNWs. We have also demonstrated the effectiveness of an additional uniaxial tensile strain in NMOS NWs down to 10nm width.

Threshold Voltage Control by Substrate Bias in 10-nm-Diameter Tri-Gate Nanowire MOSFET on Ultrathin BOX

We investigated the substrate bias effect in 10-nm-diameter tri-gate nanowire (NW) MOSFETs on ultrathin BOX. By employing a thin BOX of 20 nm and a thin NW body, a large body effect factor was achieved, which is sufficient for wide range Vth control. Ion-Ioff adjustment by Vsub of 1 V or -1 V enabled a 13% increase in Ion or a one-order decrease in Ioff, respectively. Negative Vsub could enlarge SRAM noise margin. Thus, a tri-gate NW MOSFET on ultrathin BOX is potential advantage for low power operation by adopting dynamic power and performance management.

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI) substrate is presented. Two-dimensional strain imaging demonstrates the lateral strain relaxation resulting from nanoscale patterning. An improvement of electron mobility in sSOI NW scaled down to 10-nm width is successfully demonstrated (+55 % with respect to SOI NW) due to remaining uniaxial tensile strain. This improvement is maintained even by using hydrogen annealing to form an Omega gate. For short gate length, a strain-induced <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> gain as high as +40% at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LG</i> = 45 nm is achieved for a multiple-NW active pattern.

Experimental Study of Self-Heating Effects in Trigate Nanowire MOSFETs Considering Device Geometry

Temperature rise by self-heating effects in nanowire (NW) transistors (NW Trs.) is systematically studied with respect to their dependence on the structural parameters. Temperature rise in NW Tr. is found to be independent of the NW size in sub-100-nm regions when compared at the same total power consumption. This is because the heat generated by the drain current is spread to the area larger than the NW channel. Dependences of temperature rise on other parameters such as gate oxide or buried oxide thickness suggest that heat dissipates mainly via source/drain or substrate not via the gate electrode.

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

In this letter, the electrostatic and the performance of cylindrical silicon nanowire (NW) MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated. The impact of silicon nitride (SiN) spacer thickness (7, 10, or 15 nm) on short-channel performance is examined. The tradeoff between superior electrostatic confinement and electrical performance, which will be an essential consideration for the design of future NW devices, is clearly observed. Finally, a comparison with trigate NWs shows an improved electrostatic control for a cylindrical-shaped gate, as theoretically expected.

Low-Frequency Noise in SONOS-TFT With a Trigate Nanowire Structure Under Program/Erase Operation

This letter investigates low-frequency noise (LFN) in polycrystalline silicon thin-film transistor (TFT) nonvolatile memory (NVM) under Fowler-Nordheim tunneling program/erase (P/E) operation. The NVM utilizes a silicon-oxide-nitride-oxide-silicon (SONOS)-type structure with a trigate multiple nanowire (NW) channels. The difference in the flicker noise (1/f) level between a multiple-channel NW device and a standard single-channel device became smaller after P/E cycling. The observation can be explained by the quantity of grain-boundary traps introduced by higher electric field at the NW corner during the P/E cycle, subsequently increasing the LFN level in the multiple NW SONOS-TFT.

Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Charge Trapping Layer

This study investigates the characteristics of the planar twin poly-Si thin film transistor (TFT) EEPROM that utilizes a nitride (Si3N4) charge trapping layer. A comparison is made of two devices with different gate dielectrics, one a 16 nm-thick oxide (SiO2) layer for O-structure and the other 5 nm/10 nm-thick oxide/nitride layers for O/N-structure. Incorporating a nitride charge trapping layer and reducing the tunneling oxide thickness enable the O/N-structure EEPROM to enhance the program/erase (P/E) efficiency. Additionally, EEPROM formed with the tri-gate nanowires (NWs) structure can further enhance P/E efficiency and a large memory window because of its high electric field across the tunneling oxide. Reliability results indicated that, since the nitride layer contains discrete traps, the memory window can be maintained 2.2 V after 10(4) P/E cycles. For retention, the memory window can be maintained 1.9 V, and 30% charge loss for ten years of data storage. This investigation indicates that its possibility in future system-on-panel (SOP) of thin-film transistor liquid crystal display (TFTLCD) and 3-D stacked high-density Flash memory applications.

3D-Monte Carlo study of short channel tri-gate nanowire MOSFETs

As a result of recent trends in processor speed and core temperature, III–V semiconductors have become a tempting replacement for Si in semiconductor logic. However, as device geometries shrink, the advantages of such a switch are put into question. In this paper we present a computational survey of III–V materials in a tri-gate nanowire MOSFET geometry as compared with Si to determine an optimal material choice for this geometry using a 3D semi-classical Monte Carlo simulation tool. We show that InSb and InAs show promise as future materials for next generation switching devices.

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thin-film transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after 103 P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.

Two-bit effect of trigate nanowires polycrystalline silicon thin-film-transistor nonvolatile memory with oxide/nitride/oxide gate dielectrics

This work studies the two-bit effect of trigate nanowires polycrystalline silicon thin-film transistors with silicon-oxide-nitride-oxide-silicon nonvolatile memory. The two-bit effect is clearly demonstrated by the localized charge trapping in a nitride layer. The programing operation is performed by channel hot electrons injection, and erasing is performed by channel hot holes injection. The threshold voltage shifts between forward read and reverse read schemes is 2.2V. At a large gate length of 5μm, the programing is dominated by Fowler–Nordheim tunneling, resulting in the absence of two-bit storage capacity. Regarding the two-bit programing and erasing speed characteristics, one-bit programing or erasing does not affect the other bit.

Ballistic recovery in III-V nanowire transistors

In recent years, a great deal of attention has been focused on the development of quantum wire transistors as a means of extending Moore’s law. Here the authors present results of fully three-dimensional, self-consistent quantum mechanical device simulations of InAs trigate nanowire transistor. The effects of inelastic scattering have been included as real-space self-energy terms. They find that the position of dopant atoms in these devices can lead to a reduction in the amount of scattering the carriers experience. They find that the combination of deeply buried dopant atoms and the high energy localization of polar optical phonon processes allow devices to recover their ballistic behavior even in the presence of strong inelastic phonon processes.

Degradation Behaviors of Trigate Nanowires Poly-Si TFTs with NH[sub 3] Plasma Passivation under Hot-Carrier Stress

This work studies degradation behavior after hot-carrier stress of trigate polysilicon thin-film transistors (poly-Si TFTs) with nanowires. The NH 3 plasma passivation effect is also studied on the electrical characteristics after hot-carrier stress. The reliability of poly-Si TFTs with NH 3 plasma passivation outperforms that without such passivation, resulting from the effective hydrogen passivation of the grain-boundary dangling bonds, and the pileup of nitrogen at the SiO 2 /poly-Si interface. The reliability of poly-Si TFTs further improves by using nanowires structure. These findings originate from the fact that the nanowires poly-Si TFT has robust trigate control to reduce the hot-carrier effect due to declining lateral electrical field and its penetration from the drain, and its split nanowire structure has superior NH 3 plasma passivation effect. In degradation results under dc and ac stress, it reveals that the NH 3 plasma is mostly passivated on deep traps of grain boundaries rather than tail traps.

Investigating the performance limits of silicon-nanowire and carbon-nanotube FETs

In this work we investigate and compare the electrostatics of fully depleted cylindrical silicon-nanowire (SiCNW) FETs, four-gate rectangular nanowire (4G RNW) FETs, tri-gate rectangular nanowire (3G RNW) FETs and gate-all-around carbon-nanotube (GAA-CNT) FETs at advanced miniaturization limits. In doing so, we rigorously solve the coupled Schrödinger–Poisson equations within the device cross-sections and fully account for quantum-mechanical effects. The investigation, carried out for the 65 and 45 nm technology nodes, leads to the unexpected conclusion that, for an assigned threshold voltage, the gate-all-around CNT-FET offers only a slightly better performance with respect to the SiCNW and the 4G RNW-FETs. This is due to the compensation of two different mechanisms, namely a higher gate effectiveness and a lower density of states. The 3G RNW yields instead an electron density within the channel which is about 25% lower than the SiCNW and 4G RNW-FETs at a given gate voltage. Such a reduced performance is due to its inherent asymmetry, which negatively affects the gate control on the channel charge.