Tri-gate Structure Research Articles

Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel

In this paper, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio and good short channel effect control on the channel potential. The current ratio is of ~6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> (ID) at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.1 V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> =-3, and 0 V. The relatively low OFF-current is of 6 nA/ μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.1 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> =0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =120 nm.

Corner Effect in Multiplier SOI-Fin FETs

SOI-Multi-FinFET was analyzed by a three-dimensional numerical device simulator and its electrical characteristics and potential distribution in the oxide and the silicon in the section perpendicular to the flow of the current were compared for single-fin, three-fin and five-fin FET to investigate the influence of fins number on corner effect in Dual-gate SOI Multi-FinFET, and we provide a comparison with a Tri-gate SOI Multi-FinFET structure.

Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High ${\rm I}_{\rm ON}/{\rm I}_{\rm OFF}$ Ratio Ge FinFETs

Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high ION/IOFF ratio (~5×105, at VD=0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (VTH) shift can be maintained at the level of ~110 mV/V and ~ 0.1 V, respectively, for Ge n-channel FinFET with Lchannel=120 nm and WFin=40 nm. Multifin Ge FinFET with Lchannel=170 nm and WFin=50 nm is also illustrated. Both N- and P-FinFETs possess high ION/IOFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.

Dopant-Free CMOS on SOI: Multi-Gate Si-Nanowire Transistors for Logic and Memory Applications

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.

CMOS without Doping on SOI: Multi-Gate Si-Nanowire Transistors for Logic and Memory Applications

In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.

Tri-Gate Polycrystalline Silicon Thin-Film Transistors Fabricated by Continuous-Wave Laser Lateral Crystallization with Improved Electron Transport Properties

Tri-gate channel structures were applied to polycrystalline silicon (poly-Si) thin-film transistors (TFTs) fabricated by continuous-wave (CW) laser lateral crystallization (CLC). We had two objectives in using tri-gate structures in CLC poly-Si TFTs. One was the enhancement of effective electron mobility (µeff) by using the tensile strain induced by the CLC process and the lateral-strain-relaxation effect in tri-gate structures. The other was the reduction of µeff variation caused by increasing the number of surfaces with different crystal orientations by up to a factor of three. By applying tri-gate structures to CLC poly-Si TFTs, both 8% µeff enhancement and 41% reduction of µeff variation were achieved at the surface carrier density of 5×1012 cm-2. These results are expected to be useful for the device size shrinkage of high-performance poly-Si TFT circuits.

Improving the Performance of Nanowires Polycrystalline Silicon Twin Thin-Film Transistors Nonvolatile Memory by NH3 Plasma Passivation

This study investigates the performance improvement of the polycrystalline silicon nanowires twin thin-film transistors nonvolatile memory (poly-Si NWs twin-TFT NVM) by NH3 and H2 plasma treatment. The NWs twin-TFT NVM exhibits superior gate control because its tri-gate structure provides a large memory window (ΔVth) and high program/erase (P/E) efficiency. Additionally, the proposed twin-TFT NVM scheme has effective NH3 and H2 plasma passivation efficiency due to its split nanowire channels structure. As for characteristics of transistors, passivation by both NH3 and H2 plasma increases the mobility and the Ion/Ioff ratio. Moreover, as for characteristics of NVM, they increase ΔVth, P/E speed and improve the reliability of the devices. Comparing channel hot electron (CHE) injection and Fowler–Nordheim (FN) tunneling programming mechanisms reveals that the device with NH3 plasma passivation can significantly enhance the program speed. This ability is attributed to passivation of the defects in both the grain boundaries of the poly-Si channel and the Si/SiO2 interface by hydrogen and nitrogen radicals, respectively. As for reliability results, the NH3 plasma-passivated NVM device has memory windows of 1.7 and 3.8 V after 103 P/E cycles and for ten years of data storage, respectively.

Nanowire to Single-Electron Transistor Transition in Trigate SOI MOSFETs

We investigate the effect of symmetrical geometrical constrictions on the electrical characteristics of ultrathin silicon-on-insulator nanowires with a trigate structure using a 3-D numerical quantum simulator. Introducing barriers at the source and drain junctions profoundly alter the device physics and a transition from 1-D to 0-D quantum behavior is observed. The constrictions create resonance levels in the channel region of nanowire due to confinement in the three directions of space, which, in turn, causes oscillation of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> characteristic. Based on the observed characteristics, we derive a set of parameters that draws the line between 1-D and 0-D quantum behavior of silicon nanowire transistors.

Asymmetric 3D tri-gate 4H-SiC MESFETs with a recessed drain drift region

An improved asymmetric 3D tri-gate 4H-SiC metal–semiconductor field effect transistor with a recessed drain drift region was proposed in order to improve the power and frequency performance of the device. The dc and RF electrical characteristics of the proposed structure were studied in detail by numerical simulation. The simulated results showed that the maximum theoretical output power density of the proposed structure is about 36% larger than that of the published symmetric 3D tri-gate structure due to significant improvement of saturation drain current and breakdown voltage. The cut-off frequency (fT) and the maximum oscillation frequency (fmax) of the proposed structure are 20.6 GHz and 82.4 GHz compared to 16.1 GHz and 55.9 GHz of those of the published 3D tri-gate structure, respectively.

Trigate TiN Nanocrystal Memory with High-k Blocking Dielectric and High Work Function Gate Electrode

In this work, high-performance TiN metal nanocrystal nonvolatile memories using a p + poly-Si gate and a Al 2 O 3 blocking dielectric layer with trigate structure are fabricated on silicon-on-insulator substrate. Devices with moderate transistor performance and superior memory properties are demonstrated. A memory window as high as 5 V is achieved after Program/Ease (P/E) operation at ± 10 V for 0.1 s, with only 18 and 33% charge loss at room temperature and at 85°C after 10 years storage. Only +0.5 V window shift and almost no window narrowing after 10 5 P/E operations can be obtained. Furthermore, a device with larger nanocrystals has better P/E characteristics and superior retention performance.

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thin-film transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after 103 P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied Ω- and tri-gate structures to obtain abrupt switching (3–10mV/decade) combined with a hysteresis in the ID(VDS) and ID(VGS) characteristics. The PIMOS device shows an extraordinary temperature stability up to 125°C. The influence of various parameters on device performance as abrupt switch or memory cell is investigated. Reduction of the electrical channel length, i.e. of gate length and/or substrate doping, reduces the breakdown voltage and hence the DRAM operating voltage, but also increase the Ioff. Two architectures for a capacitor-less DRAM cell are demonstrated and evaluated. In addition, a PIMOS n-type hysteretic inverter is demonstrated, which may serve as a 1T SRAM cell.

A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory

In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) , and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.

Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure

In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon–oxide–nitride–oxide–silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V th shift is improved from − 0.3 V to − 1.3 V at − 14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 °C and a 0.8 V memory window after 5 × 10 3 P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display.

Simulation of high-power 4H-SiC MESFETs with 3D tri-gate structure

A novel 3D tri-gate 4H-SiC MESFET structure is proposed for high-power RF applications. In comparison with the conventional structure, improved saturation drain current is obtained owing to the formation of a vertical channel, which induces device equivalent channel width increase. The output power density of the proposed structure with t=2 µm, a=0.4 µm and w=0.6 µm is 15.5 W/mm compared to 4.2 W/mm for the conventional one and yet it maintains almost the same cutoff frequency (fT) and maximum oscillation frequency (fmax).

Effects of Channel Width on Electrical Characteristics of Polysilicon TFTs With Multiple Nanowire Channels

This brief studies the electrical characteristics of a series of polysilicon thin-film transistors (poly-Si TFTs) with different numbers of multiple channels of various widths, with lightly doped drain (LDD) structures. The nanoscale TFT with ten 67-nm-wide split channels (M10) has superior and more uniform electrical characteristics than other TFTs. Additionally, experimental results reveal that the electrical performance of proposed TFTs enhances with each channel width decreasing, yielding a profile from a single-gate to tri-gate structure.

Plasma doping technology for fabrication of nanoscale metal-oxide-semiconductor devices

We developed a plasma doping (PLAD) technique which is appropriate for the nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs) fabrications. Silicon-on-insulator (SOI) n-MOSFETs with a 50-nm-length metal gate and a 100-nm-channel width were successfully fabricated. The source and drain extensions (SDE) of SOI n-MOSFETs were formed using a plasma doping technique. The advantage of this process is the exclusion of additional activation annealing after introduction of impurity in SDE, which resulted in a laterally abrupt source/drain (S/D) junction profile. We can obtain a low sheet resistance by the PLAD technique and low damaged shallow junctions. A trigate structure SOI n-MOSFET with a gate length of 50nm fabricated by high-temperature plasma doping revealed suppressed short-channel effects.

A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performance

A simple and manufacturing worthy method to pattern a very thin channel body of the FinFET/Tri-gate MOSFET is presented. A channel body as thin as 40 nm using the phase-shift mask (PSM) technique with deep UV 248 nm lithography on UV 210 Shipley resist has been achieved, while having an inherently wider Source/Drain (S/D) extension region. The width of extension region was optimized using the Prolitho.3D lithography simulator for the exposure dose and reticle bias conditions. The device simulation of the wider S/D extension region performed using three-dimensional (3-D) Davinci device simulator shows the significant reduction in the S/D parasitic resistance. Furthermore, these patterns on photoresists like UV 210 provides the basis for the easy integration to the mainstream CMOS technology, hence the potential for manufacturability with higher device performance.

Fabrication of 50-nm Gate SOI n-MOSFETs Using Novel Plasma-Doping Technique

A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.