Trench MOSFET Research Articles

A low gate charge field-plate trench MOSFET with hollow split gate structure

We propose a high-performance field-plate trench MOSFET featuring hollow split gate structure in this paper. By reducing the overlap of control gate to split gate without additional masks and preserving the stepped split gate structure, it is confirmed that the parasitic gate capacitance and gate charge are significantly reduced without changing the control gate structure and influencing the electric field distribution of drift region. Compared with the conventional two-step-oxide field-plate trench MOSFET, TCAD numerical simulation results show that gate-source charge (Qgs) and gate charge (Qg) (Vgs = 10 V) of the proposed device with a breakdown voltage of 94.32 V are reduced by 20.94% and 13.59%, respectively. Besides, breakdown voltage (VB) and specific on-resistance (Ron,sp) of the proposed device remain almost constant because of the retained sidewall of hollow split gate. In addition, it is observed that the average total power loss of the proposed device is reduced by 4.60%–8.06% when frequency ranges from 100 kHz to 1 MHz in comparison to that of the conventional one.

A Low-Loss Diode Integrated SiC Trench MOSFET for Improving Switching Performance

A novel silicon carbide (SiC) asymmetric trench MOSFET with integrated low-loss diode (LLD-ATMOS) is proposed and investigated by numerical simulations to reduce switching loss and eliminate bipolar degradation of body diode. The N-channel region beneath the dummy gate provides a low barrier path to transport electrons form the N-drift layer to N+ source region, with the result that the forward conduction voltage drop is reduced from 3.5 V at 10 A of the pn body diode to 1.9 V at 10 A of the LLD-ATMOS. Furthermore, the reverse recovery charge (QRR) of LLD and the gate-to-drain capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gd}}$ </tex-math></inline-formula> ) of LLD-ATMOS are 76% and 95% lower than those of the conventional asymmetric trench MOSFET (C-ATMOS). As a result, the turn-off and turn-on losses of LLD-ATMOS are reduced by 49% and 58%, respectively. The calculated high-frequency figure of merit ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {HF-FOM} = {R}_{ {{\text{ON}}},\text {sp}} \times {C}_{\text {gd}}$ </tex-math></inline-formula> ) of LLD-ATMOS is tremendously decreased to one-fourteenth of the value of C-ATMOS. In addition, a conduction band energy analysis model for the LLD is developed. The improved performances suggest that LLD-ATMOS is a competitive option in power electronic systems.

Comparison of Commercial Planar and Trench SiC MOSFETs by Electrical Characterization of Performance-Degrading Near-Interface Traps

The suboptimal performance and low channel-carrier mobility of silicon carbide (SiC) power MOSFETs are attributed to a high density of oxide traps near the 4H-SiC/SiO2 interface. In this article, a commercial 1200-V SiC trench MOSFET has been compared with a planar MOSFET obtained from the same manufacturer. We employed a newly developed integrated-charge method to quantify the near-interface traps (NITs). The results reveal that, at operating gate voltages, 15% of the total channel electrons were trapped for longer than 500 ns in the planar MOSFET compared to 9% in the trench MOSFET.

Investigation of a 4H-SiC Trench MOSFET with Back-Side Super Junction.

In this paper, a 4H-SiC trench gate MOSFET, featuring a super junction layer located on the drain-region side, is presented to enhance the breakdown voltage and the figures of merit (FOM). The proposed structure is investigated and compared with the conventional structure with a 2D numerical simulator—ATLAS. The investigation results have demonstrated that the breakdown voltage in the proposed structure is enhanced by 21.2%, and the FOM is improved by 39.6%. In addition, the proposed structure has an increased short-circuit capability.

Origin of trap assisted tunnelling in ammonia annealed SiC trench MOSFETs

The interface between silicon carbide (SiC) and silicon dioxide (SiO2) is of considerable importance for the performance and reliability of 4H-SiC (trench) metal oxide semiconductor field effect transistors (MOSFETs) and various different post oxidation anneals (POAs) have been used to optimize its quality. Whereas nitric oxide (NO) POA leads to very reliable and well performing MOSFETs, ammonia (NH3) can further improve the device performance, however, at the cost of the gate oxide (GOX) reliability, e.g. leading to trap assisted tunneling (TAT). We investigate the origin of TAT and GOX leakage in differently annealed gate oxides experimentally, using 4H-SiC trench MOSFETs, and theoretically, using Density Functional Theory (DFT) simulations. Our findings reinforce the view that the NO anneal for SiC devices results in the best overall quality as devices annealed in NH3 and nitrogen N2 show higher oxide charge density and leakage currents. DFT simulations demonstrate that, contrary to what has often been assumed so far, NH3 annealing leads to the formation of additional hydrogen related defects, which open leakage paths in the oxide otherwise not present in NO treated oxides.

Significant Improvement of Switching Characteristics in a 1.2‐kV SiC SWITCH‐MOS by the Application of Kelvin Source Connection

Here we show, for the first time, a significant improvement of switching characteristics in a 1.2‐kV SiC Schottky barrier diode‐wall integrated trench MOSFET (SWITCH‐MOS) by the application of a Kelvin source (KS) connection. Turn‐on loss (Eon) was greatly reduced, with superior Eon‐dVDS/dt trade‐off characteristics at a moderate dVDS/dt value of about 10 kV/μs, because the SWITCH‐MOS with KS achieves a more suppressed peak reverse recovery current in embedded Schottky barrier diodes even at a higher dID/dt during the turn‐on operation than a state‐of‐the‐art SiC trench MOSFET with KS. This feature is a peculiarity of the SWITCH‐MOS when the KS connection is applied. Notably, measured and calculated results confirmed that the SWITCH‐MOS with KS had less dissipated turn‐off loss, especially in a second half of turn‐off regions (Region 2), than the SWITCH‐MOS w/o KS. However, owing to a higher negative turn‐off dID/dt, the MOSFET with KS has a larger drain surge voltage. With an optimum gate resistance, the SWITCH‐MOS with KS has 8% less total switching loss than a SWITCH‐MOS without KS, and 29% less than a state‐of‐the‐art SiC trench MOSFET with KS, while keeping a moderately low dVDS/dt of 10 kV/μs and suppressing a drain peak voltage of &lt;720 V. © 2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

TCAD-Based Investigation of a 650 V 4H-SiC Trench MOSFET with a Hetero-Junction Body Diode.

In this paper, a 650 V 4H-SiC trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a hetero-junction diode (HJD) and double current spreading layers (CSLs) is proposed and studied based on Sentaurus TCAD simulation. The HJD suppresses the turn-on of the parasitic body diode and improves the performance in the third quadrant. CSLs with different doping concentrations help to lower the on-state resistance as well as the gate-drain capacitance. As a result, the on-state resistance is decreased by 47.82% while the breakdown voltage remains the same and the turn-on and turn-off losses of the proposed structure are reduced by 83.39% and 68.18% respectively, compared to the conventional structure.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate (SG), and p-type pillar (p-pillar) surrounded thick oxide shielding region (GSDP-TMOS) is investigated by Silvaco TCAD simulations. The source-connected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge (Q gd,sp) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage (BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance (R on,sp) becomes smaller. In the end, comparing with the bottom p+ shielded trench MOSFET (GP-TMOS), the Baliga figure of merit (BFOM, BV 2/R on,sp) is increased by 169.6%, and the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp) is improved by 310%, respectively.

(Invited) Vertical Gallium Nitride Mosfets for Electric Drivetrains

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. For electric vehicle drivetrains, this translates to higher efficiency and power density, resulting in more miles driven per charge. This move towards wide-bandgap power electronics is necessary to achieve the U.S. Department of Energy (DOE) power electronics density target of 100 kW/L.Vertical gallium nitride-based power devices are expected to exceed Si and even SiC-based systems with the promise of increased performance and power density. Compared to lateral GaN devices, a vertical topology promotes more efficient scaling towards high-power applications, where both high voltage and high current are necessary. This talk describes our team’s effort towards developing vertical GaN MOSFETs. The results of Sandia’s first-generation device demonstrator serve as a milestone in the path of producing devices rated for 1200-V and 100-A operation.The vertical GaN trench MOSFET is unique compared to Si- or SiC-alternatives in that the doped layers comprising the source and body regions are grown by epitaxy rather than formed by ion implantation. Challenges with selective-area doping in GaN add additional complexity to the design of a trench MOSFET. In addition, the lack of a high-quality native oxide in GaN means that the gate dielectric must be deposited rather than thermally grown. The devices produced at Sandia rely on atomic-layer-deposited thin films for the gate dielectric (primarily Al2O3 or SiO2). First-generation results demonstrate devices capable of 400 mA/mm drain current, 108 on/off ratio, and a positive threshold voltage near 8 V. More recently, devices capable of blocking 500 V in the off-state have been demonstrated. Device failure in the off-state results from high fields in the gate dielectric, which can be minimized by reducing the trench etch depth or by increasing the voltage rating of the drift region. However, further shielding of the gate dielectric to achieve substantially higher off-state voltages requires significant changes to the device architecture which are reliant on selective-area doping. In addition, device-killing defects either from the starting substrate, the epitaxy, or defects introduced during processing limit yield for large-area devices and present a substantial obstacle to scale devices for high-current operation. Hence, methods for reducing cell pitch and increasing packing density are highly valued. In this talk, we will discuss the path forward for achieving higher breakdown voltages and high-current operation using GaN-specific strategies to achieve better performing devices, as well as some of the challenges for vertical GaN development. This work provides a foundational platform for developing next-generation power electronics that employ wide bandgap, gallium nitride semiconductors. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

Unclamped Inductive Switching Robustness of SiC Devices With Parallel-Connected Varistor

Unclamped inductive switching (UIS) robustness of SiC devices with parallel-connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers (SSCBs). Because the operation of UIS tests is similar to that in the interruption of SSCBs, UIS tests of SiC devices without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC devices with the varistor was much larger than that without varistor. The effect of varistor on the increase of cutoff current depended on the device type and rating current. The cutoff current was 3–6 times higher for planar MOSFETs and 5–10 times higher for trench MOSFETs compared with no varistor condition. In contrast, the effect of varistor for JFET was small because the gate drive condition strongly affected the current switching time from SiC-JFET to varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection because the destruction mechanism of SiC devices was changed because of the change in self-heating timing during the UIS.

Benchmarking the robustness of Si and SiC MOSFETs: Unclamped inductive switching and short-circuit performance

The reliability and robustness of power devices are key areas of research for increasing the adoption of wide bandgap power semiconductors. This paper benchmarks the robustness under short-circuit (SC) and unclamped inductive switching (UIS) of 650 V SiC trench MOSFETs, SiC planar MOSFETs and silicon super-junction MOSFETs. The performance is characterised at 75 °C and 150 °C and the results show that the SiC MOSFETs have reduced temperature sensitivity under both SC and UIS conditions, which will be beneficial from the application point of view. In the case of the silicon MOSFET, increasing the temperature enhances the short-circuit withstand time as the peak short-circuit current is reduced. The opposite trend is observed for UIS, with a reduction of robustness as the temperature is increased. The absolute SC and avalanche energies are lower for the SiC MOSFETs, but if the chip areas are considered, the energy densities are higher in the SiC MOSFETs, with the SiC Trench having a superior critical SC energy and the SiC planar having a higher avalanche energy density. The higher critical SC and UIS energy densities in SiC MOSFETs, together with their higher thermal resistances result in higher peak junction temperatures and clear hotspots are identified using Finite Element simulations.

Performance Assessment of a New Radiation Microsensor Based 4H-SiC trench MOSFET: A Simulation Study

Performance Assessment of a New Radiation Microsensor Based 4H-SiC trench MOSFET: A Simulation Study

Failure Mechanism of Aluminum Diffusion in Low-Voltage Trench MOSFET With High Cell Density

In this paper, a low-voltage trench metal oxide semiconductor field effect transistor (MOSFET) with high cell density is researched on the process design. The experimental device pitch is reduced to 0.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> by three-dimensional (3-D) design of P plus region and self-aligned process, while the contact between silicon and metal is convex rather than the concave in conventional trench MOSFET. BV failure was founded because of the particularity of this structure and the failure is caused by the diffusion of aluminum (Al) into the drift region during the final alloy step in the metal forming process. This paper reveals the mechanism of Al / Silicon (Si) double diffusion and presents the refined surface metal film, which can suppress reverse diffusion and forward diffusion simultaneously. The risk of failure is reduced and functional devices are obtained by the application of the proposed surface metal film. Furthermore, it is recommended to use TiN layers in a total 50 nm as the barrier layer in the metallization process to provide a certain diffusion length and the fabricated device achieves a low specific on-resistance of 3.58 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a corresponding breakdown voltage of 26.2 V eventually.

Recent progress on the vertical GaN power transistor and its integrated circuit

<p indent="0mm">Silicon (Si) material is the mainstream semiconductor material for a long time because of its relatively excellent high-temperature resistance, radiation resistance, low price, and huge reserves. However, with the rapid development of power electronics technology, the development of technology has reached a bottleneck period, and Moore’s law has gradually failed. The existing silicon-based semiconductor devices are close to the theoretical limit of Si materials and can no longer meet the performance requirements of future power devices. However, the cost of transistors is constantly rising, and the performance improvement is slow, gradually moving towards the post-Moore era. To further improve the performance of the device, it is necessary to seek new technologies or new materials to support the continuous development of power devices, and the core of the progress of power semiconductor devices is the development of semiconductor materials. As the third generation of wide band gap semiconductors, gallium nitride (GaN) has been superior to Si in terms of material properties. GaN has the advantages of a wide band gap, high critical field strength, high electron saturation velocity, high conductivity, high-temperature resistance, and high voltage resistance. Compared with traditional Si-based power devices, it not only has higher breakdown voltage, low on-resistance, high electron mobility and good thermal conductivity, but also has smaller device volume and better heat dissipation performance under the same performance, which greatly reduces power consumption and achieves the effect of energy saving and emission reduction. The cost of early GaN single crystal preparation and epitaxial growth is beyond reach. However, with the mature development of growth technology, not only the cost of GaN single crystal substrate and its epitaxial growth is decreasing, but also the quality is gradually increasing, which lays a solid foundation for the wide application of GaN power devices in the future. This paper lists the main physical parameters of GaN and other semiconductor materials, the preparation of GaN single crystal, and the main methods of its epitaxy growth, and describes the advantages of GaN power devices in the current environment. For the device structure, the problems of the lateral device and the advantages of the vertical device are listed, and why the vertical device can become the mainstream structure of future power devices is explained. On this basis, the structure, working principle, research progress, and existing problems of vertical current aperture GaN transistor (CAVET), trench GaN MOSFET, vertical trench MOSFET based on <italic>in-situ</italic> oxidation GaN interlayer (GaN OG-FET), and vertical GaN fin field effect transistor (GaN FinFET) are introduced in detail. The performance parameters of vertical GaN power transistors mentioned in this paper are summarized in tables according to device types and time sequence, and the general direction of the development of GaN power transistors in the future is proposed. For integrated circuit systems, the special requirements and key technologies of GaN power devices in driver chips are summarized. Finally, for the current market environment, listing the vertical GaN power transistor in the medium and low voltage range is a more popular and promising application scenario.

A 4H–SiC double trench MOSFET with split gate and integrated MPS diode

A 4H–SiC double trench MOSFET with split gate and integrated MPS(Merged PiN Schottky) diode (MPS-SGMOS) is proposed, and simulated by Sentaurus TCAD tools. The introduction of the P+ shielding region ensures the reliability of the gate oxide of the device, reduces the electric lines of force gathered at the bottom of the gate oxide, and improves the withstand voltage of the device; the introduction of the Schottky diode enables the device to obtain better reverse recovery performance; adding a source electrode between the split gate reduces the Cgd greatly and the switching losses of the device, so that the device is more suitable for high frequency applications. As a result, comparing to conventional double-trench MOSFET (Con-DTMOS), MPS-SGMOS owns comparable on-state characteristics, while its breakdown voltage is increased by 10.5%. The FOM(figure of merit) of Ron,sp × Qgd, sp is decreased by 78.2% compared to the traditional device, moreover the peak reverse recovery charge is decreased by 32.7%.

Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

In this work, characteristics of trench sidewall capacitance were investigated in a 4H-SiC stepped thick-oxide (STO) trench metal–oxide–semiconductor (MOS) structure. Multigroup SiC trench MOS capacitor test patterns with different structures and geometric parameters were designed and fabricated. From the capacitance–voltage measurements, the characteristics of the described SiC STO trench MOS were calculated and analyzed, including the thicknesses of the oxide at different locations in trench, the position of the oxide step at trench sidewall, and the flat-band voltages as well as the oxide charge densities of MOS from the upper part and lower part of oxide step at trench sidewall. Results showed that the flat-band voltages of MOS from the upper part (10.2 V) and lower part (12.5 V) of trench sidewall step had pronounced positive shifts over the ideal flat-band voltage (0.36 V), indicating a massive negative charges in the sidewall oxide film. Meanwhile, the net oxide charge density of MOS from the lower part of sidewall step ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 0.92\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ) was smaller than that from the upper part ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 2.41\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ), which was likely attributed to the massive shallow states in the oxide and to the poor quality of the thick-oxide film grown via chemical vapor deposition technology. The present works are providing a convenient technology to monitor the trench MOS structure by measuring the capacitance during SiC trench MOSFETs fabrication.

(Invited) Breakthrough Avalanche and Short Circuit Robustness in Vertical GaN Power Devices

After decades of relentless efforts, GaN power devices, specifically, the lateral GaN high-electron mobility transistor (HEMT), have been commercialized in the 15-650 V classes. Owing to GaN’s competitive physical properties over Si and SiC for power electronics, GaN HEMTs allow for higher switching frequency and therefore, have already seen wide adoptions in fast chargers, wireless charging, data centers, and electrified transportation. Despite the success of lateral GaN HEMTs, a vertical device structure is usually believed to be more favorable for high-voltage, high-power devices. In the last few years, with the advent and maturity of large-diameter, low-dislocation GaN wafers on freestanding GaN substrates, a new generation of vertical GaN power devices have been developed to extend GaN’s application space beyond 650 V. Very recently, several industrial vertical GaN devices in the voltage classes of 1.2-1.7 kV have been demonstrated, which are close to commercialization.This presentation will review the key advancements in vertical GaN power devices in the past decade, with a focus on the device technologies that are being commercialized, and provide a prospective for research and development in the next decade. The devices to be covered will include two-terminal power rectifiers including the p-n diodes, Schottky barrier diodes, junction barrier Schottky diodes, and trench MIS/MOS barrier Schottky diodes. The transistors will include the trench and planar MOSFETs, current-aperture vertical electron transistors, fin-channel MOSFETs, and fin-channel JFETs. Particular emphasis will be on large-area rectifiers and transistors with a device performance superior to similarly-rated Si and SiC transistors. The newly demonstrated avalanche and short-circuit robustness in vertical GaN devices, which are lacking in lateral GaN HEMTs, as well as their underlying device physics, will also be introduced. The presentation will be concluded by a discussion of current challenges and future application spaces of vertical GaN devices, as well as emerging vertical GaN devices (e.g., superjunction) under development.

Vertical GaN trench MOSFETs with step-graded channel doping

Vertical GaN trench MOSFETs have shown enormous potential for efficient power switching applications. Low ON-resistance (RON) to minimize power loss, high output current (ION) to maximize driving capability, and large threshold voltage (Vth) to avoid false turn-on are highly desirable. This work reports vertical GaN trench MOSFETs with step-graded channel doping. Conventional devices with uniform channel doping were involved for comparison. The experimental results show that step-graded channel doping can achieve an improved trade-off between ION, RON, and Vth than uniform channel doping.

SiC Mass Commercialization: Present Status and Barriers to Overcome

In an increasingly electrified technology driven world, power electronics is central to the entire clean energy manufacturing economy. Silicon (Si) power devices have dominated power electronics due to their low cost volume production, excellent starting material quality, ease of fabrication, and proven reliability. Although Si power devices continue to improve, they are approaching their operational limits primarily due to their relatively low bandgap, critical electric field, and thermal conductivity that result in high conduction and switching losses, and poor high temperature performance. Silicon Carbide’s (SiC) compelling efficiency and system benefits have led to significant development efforts over the last two decades and today planar and trench MOSFETs, and JFETs are commercially available from several vendors as discrete components or in high power modules in the of 650 V to 1700 V voltage range. High impact application opportunities, where SiC devices are displacing their incumbent Si counterparts, have emerged and include automotive and rail power electronics with reduced losses and reduced cooling requirements; novel data center topologies with reduced cooling loads and higher efficiencies; variable frequency drives for efficient high power electric motors at reduced overall system cost; more efficient, flexible, and reliable grid applications with reduced system footprint; and “more electric aerospace” with weight, volume, and cooling system reductions contributing to energy savings. In particular, SiC insertion in electric vehicles brings major competitive advantages and is a volume application opportunity that can spur manufacturing economies of scale and lower system costs. As SiC continues to grow, the industry is lifting the last barriers to mass commercialization that include higher than Si device cost, relative lack of wafer planarity, the presence of basal plane dislocations, reliability and ruggedness concerns, and the need for a workforce skilled in SiC power technology to keep up with the rising demand. It should be noted that in many applications, insertion of SiC reduces overall system cost compared to Si even though SiC devices can cost 2-3 more than their Si counterparts. This is due to the passive component and cooling system simplifications enabled by the efficient high frequency SiC operation. In this paper, we will review key aspects of SiC technology and discuss overcoming barriers to mass commercialization.

Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

SiC MOSFETs have already replace silicon-based device in power applications, even if some technological issues are still not solved. The most important of them is related to the complex traps distribution at SiC/SiO2 interface. Interface traps affect the overall device behavior, modifying channel mobility and introducing hysteresis. In this work experimental C-V and I-V curves are carried out on various commercial SiC MOSFET at different temperatures. The focus is the comparison of hysteresis arising in trench and planar SiC MOSFETs.