Trench Dynamic Random Access Memory Research Articles

Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization

The dependence of dynamic random access memory (DRAM) device performance on trench and stack cell structures was first observed by changing the process position of passivation annealing. For the trench DRAM, the data retention fail bit counts (FBCs) decreased by 18% and the cell transistor threshold voltage (CTVth) shift by 53 mV. The FBCs are primarily influenced by the junction leakage current. In contrast, for the stack DRAM, the data retention FBCs increased by 225% and the CTVth shift increased by 20 mV. The FBCs are primarily influenced by the gate-induced drain leakage (GIDL) current because of the large gate and the drain overlap region in the recess channel array transistor (RCAT). The interface states increased after the deposition of the plasma nitride layer, as observed in the charge pumping measurement in the trench DRAM. Transmission electron microscopy indicated that the gate oxide thickness in the bottom region of the RCAT is thinner to generate gate oxide leakage. Furthermore, a decrease in the activation energy from 0.64 to 0.55 eV implies the occurrence of GIDL current, which corresponds to the FBC analysis result. This paper demonstrated that the passivation annealing position requires careful adjustment for device and manufacturing optimization.

Implementation of Electrochemical Methods for Metrology and Analysis of Nano Electronic Structures of Deep Trench DRAM

In the course of feasibility study the necessity of implementing electrochemical methods as an inline metrology technique to characterize semiconductor nano structures for a Deep Trench Dynamic Random Access Memory (DT-DRAM) (e.g. ultra shallow junctions USJ) was discussed. Hereby, the state of the art semiconductor technology on the advantages and disadvantages of the most recently used analytical techniques for characterization of nano electronic devices are mentioned. Various electrochemical methods, their measure relationship and correlations to physical quantities are explained. The most important issue of this paper is to prove the novel usefulness of the electrochemical micro cell in the semiconductor industry.

DRAM Data Retention and Cell Transistor Threshold Voltage Reliability Improved by Passivation Annealing Prior to the Deposition of Plasma Nitride Layer

We report, for the first time, that the fail bit counts of dynamic random access memory (DRAM) reduced by 18% and the yield loss after packaging induced by data retention degradation decreased by 1.16% for a trench DRAM cell; this reduction was attributed to a change in the process position of passivation annealing. Moreover, the cell transistor threshold voltage (CTVth) shift was reduced to 53 mV, and the uniformity of the CTVth was improved from 100 to 38 mV; this provided the DRAM cell with a large margin for further reducing both the dose of the threshold implant and the electrical field. We proposed a possible mechanism of carrying out passivation annealing prior to the deposition of a plasma nitride layer in order to increase the supply of hydrogen for the passivation of the crystalline defects as well as improving data retention. The CTVth was increased by breaking of weak Si-H bonds by plasma charging during the deposition of the plasma nitride layer. Data retention degradation after the packaging process ( ~ 250°C) reduced because of the presence of a number of strong Si-H bonds, indicating the presence of a greater number of interface trap states near the storage trench than near the bit line, as observed in the case when hot-carrier stress was applied under two conditions. Results of data retention analysis show that the fail bit counts are primarily influenced by the junction leakage current and not the gate-induced drain leakage current. Above observation is dependent on device process flow, which provided us an easy way for DRAM device optimization and maximized manufacturing process window.

Impact of Organic Contamination From Partially Fluorinated O-Ring in High-Temperature Nitride Process on DRAM Performance

This paper is concerned with organic contamination from a partially fluorinated o-ring used in a furnace for a high-temperature process. The organic outgas was confirmed by Fourier transform infrared analysis of the furnace exhaust gas. Experiments from practical trench dynamic random access memory disclosed that outgassed organic contaminants from the nitride process would severely worsen the tunneling leakage current performance of the storage dielectric and lead to fatal yield loss even though the cell capacitance was almost uninfluenced. To eliminate this yield detractor requires several test runs prior to real production after installation of the partially fluorinated o-ring; otherwise, a fully fluorinated o-ring is needed. From a cost viewpoint, the latter is highly suggested.

Effects of TiCl4-Based PECVD-Ti/CVD-TiN Barrier Layers on the BF2-Doped Si for Contact Plug Technology

We have performed the investigation of Ti/TiN barrier layers deposited by PECVD of Ti and CVD of TiN using TiCl4 as a reactant on a heavily boron doped Si substrate. High contact resistance arose from both the boron out-diffusion, and high chlorine content in the Ti film with respect to the relatively high, and low process temperatures of PECVD-Ti deposition, respectively. In the optimized PECVD-Ti process condition with the satisfied boron dose in the Si substrate, comparable yields can be achieved with that using the 110nm deep trench Dynamic Random Access Memory (DRAM) technology with PVD-Ti method. Furthermore, using PECVD-Ti/CVD-TiN method for the contact metallization, it can obtain a uniform thickness of liner in the hole-type contact with aspect ratio to 6.

Synchrotron radiation x-ray photoelectron spectroscopy study on the interface chemistry of high-k PrxAl2−xO3 (x=0–2) dielectrics on TiN for dynamic random access memory applications

Engineered dielectrics combined with compatible metal electrodes are important materials science approaches to scale three-dimensional trench dynamic random access memory (DRAM) cells. Highly insulating dielectrics with high dielectric constants were engineered in this study on TiN metal electrodes by partly substituting Al in the wide band gap insulator Al2O3 by Pr cations. High quality PrAlO3 metal-insulator-metal capacitors were processed with a dielectric constant of 19, three times higher than in the case of Al2O3 reference cells. As a parasitic low dielectric constant interface layer between PrAlO3 and TiN limits the total performance gain, a systematic nondestructive synchrotron x-ray photoelectron spectroscopy study on the interface chemistry of PrxAl2−xO3 (x=0–2) dielectrics on TiN layers was applied to unveil its chemical origin. The interface layer results from the decreasing chemical reactivity of PrxAl2−xO3 dielectrics with increasing Pr content x to reduce native Ti oxide compounds present on unprotected TiN films. Accordingly, PrAlO3 based DRAM capacitors require strict control of the surface chemistry of the TiN electrode, a parameter furthermore of importance to engineer the band offsets of PrxAl2−xO3∕TiN heterojunctions.

A method to monitor the quality of ultra-thin nitride for trench DRAM with a buried strap structure

A new approach to monitor the quality of an ultra-thin nitride film has been proposed. The nitride quality is monitored by observing the oxide thickness for the nitride film after wet oxidation since the resistance to oxidation strongly depends on its quality. To obtain a stable oxide thickness without interference from extrinsic factors for process monitoring, monitor wafers without dilute HF solution clean are suggested because the native-oxide containing surface is less sensitive to oxygen and therefore forms the nitride film with stable quality. In addition, the correlation between variable retention time (VRT) performance of a real dynamic random access memory (DRAM) product and oxide thickness from different nitride process temperatures can be successfully explained and this correlation can also be used to establish the appropriate oxide thickness range for process monitoring.

Oxide-Nitride Storage Dielectric Formation in a Single-Furnace Process for Trench DRAM

A simplified and integrated technique has been proposed to form an oxide/nitride storage dielectric in a single-furnace process by low-pressure oxidation and nitride film deposition with an extra N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sub> O treatment for the trench dynamic random access memory (DRAM). Compared to the conventional nitride/oxide dielectric, this newly developed dielectric enjoys cell-capacitance-enhancement factor as high as 12.5% without degrading the leakage current and electron-trapping property. From the reliability test, the qualification for the DRAM application is also proven by the dielectric lifetime longer than 10-years. Most importantly, this technique can reduce the production cycle time without an additional equipment investment, which is essential in the cost-competitive DRAM arena

Improved Electrical Characteristics of NO-Based Storage Dielectric by N[sub 2]O Wet Oxidation and Postoxidation Treatment for Trench DRAM

A newly developed storage dielectric was found to have exceptional competence to prolong the life span of existent NO-based dielectrics by adopting N 2 O wet oxidation and postoxidation treatment. Compared with the conventional NO dielectric, 12.6% cell capacitance enhancement can be achieved while keeping a comparable leakage current. The reliability performance is also qualified with less than 438 ppm failure rate after 10-years of operation. In addition to the distinguished electrical characteristics, the intriguing point is its process simplicity since the N 2 O-related process could be fully integrated into the current furnace process. Combining the promising properties, this economical technique would be favorable for dynamic random access memory (DRAM) manufacturers to control their chip cost in the increasingly competitive arena.

A Novel Trench Capacitor Enhancement Approach by Selective Liquid-Phase Deposition

For the first time, a novel and simple trench bottle integrated process is demonstrated on dynamic random access memory (DRAM) manufacturing by selective liquid phase deposition (S-LPD) oxide. After photoresist (PR) filled into a deep trench (DT) and was recess etched at around 1.3 /spl mu/m depth, LPD oxide can be selected as a deposit onto the DT sidewall but not as a deposit on the PR surface. This S-LPD oxide is formed by using hexa-fluosilic acid (H/sub 2/SiF/sub 6/) and water without H/sub 3/BO/sub 3/. After the PR is removed, the LPD oxide becomes a protective layer on DT upper portion. Thus, the DT bottom area can be enlarged to form a trench bottle by NH/sub 4/OH wet etching. Compared to conventional DT trench, 20% of capacitance was enhanced by this S-LPD process. This novel and low-cost method is for the first time demonstrated on 200-mm wafer 110-nm trench DRAM technology.

Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAM

Conventional nitride/oxide (NO)-based storage dielectric has been demonstrated to possess the capability to extend its employment in trench dynamic random access memory (DRAM) by additional NH/sub 3/ nitridation and in situ N/sub 2/O reoxidation. Through this technique, cell capacitance could be enhanced by 12.2% as compared with NO dielectric while preserving tunneling current below 1 fA/cell. Even with NH/sub 3/ nitridation and consequent well-known introduction of electron traps, the great improvement in tunneling leakage and reliability are exhibited after N/sub 2/O treatment. With prominent electrical properties, this technique proves its eligibility for next-generation DRAM before the maturity of introduction of high-/spl kappa/ material into production.

Logic-based eDRAM: Origins and rationale for use

The IBM logic-based eDRAM (embedded DRAM) technology integrates a trench DRAM (dynamic random access memory) storage-cell technology into a logic-circuit technology, merging the two previously separate technologies. Since its introduction in the 1970s, the DRAM technology has been driven by cost while the logic technology has been driven by speed, leading to an ever-widening gap between slower memory and faster logic devices. That has led to the need for increasingly complex levels of memory hierarchies, resulting in considerable degradation of system performance despite many design and architecture compromises. DRAM can provide six to eight times as much memory as SRAM (static random access memory) in the same area, but has been too slow to be used at any cache level. Our studies, highlighted in this paper, indicated that the use of logic-based DRAM could resolve that difficulty--and was necessary for integrating systems on a chip. This has led to the inclusion of logic-based eDRAM as a memory option in the IBM ASICs (application-specific integrated circuits) product.

TLM: a trench leakage monitor for a four megabit SPT DRAM technology

The authors discuss a single trench capacitor macro-array structure used for trench dynamic random access memory (DRAM) device design and characterization, and as a manufacturing test vehicle. A nonaddressable array of trench-capacitor DRAM cells is used for quantification of trench DRAM leakage parameters, storage node parasitic device characterization, and silicon defects. Used with an addressable functional monitor, it is found to be a valuable semiconductor process development vehicle to achieve functionality and cell retention yield for a 4-Mb CMOS DRAM technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>