Trench Devices Research Articles

Temperature-Dependent Evaluation of Commercial 1.2 kV, 40 mΩ 4H-SiC MOSFETs: A Comparative Study between Planar, One-Side Shielded Trench, and Double Trench Gate Structures

This research investigates the static and dynamic characteristics of 4H-Silicon Carbide (SiC) MOSFETs with different gate structures: planar (Device A), one-side shielded trench (Device B), and double trench (Device C). We analyze threshold voltage, on-state resistance, transconductance, gate-to-source capacitances, and reverse transfer/miller capacitances with gate bias. Additionally, non-linear charges, including input charge, miller plateau, and total gate charge, are examined. Switching losses are assessed over a temperature range of 25° C to 125° C. Our findings reveal distinct performance differences, offering valuable insights for optimizing SiC MOSFETs in electric vehicle applications.

An Investigation of Body Diode Reliability in Commercial 1.2 kV SiC Power MOSFETs with Planar and Trench Structures.

The body diode degradation in SiC power MOSFETs has been demonstrated to be caused by basal plane dislocation (BPD)-induced stacking faults (SFs) in the drift region. To enhance the reliability of the body diode, many process and structural improvements have been proposed to eliminate BPDs in the drift region, ensuring that commercial SiC wafers for 1.2 kV devices are of high quality. Thus, investigating the body diode reliability in commercial planar and trench SiC power MOSFETs made from SiC wafers with similar quality has attracted attention in the industry. In this work, current stress is applied on the body diodes of 1.2 kV commercial planar and trench SiC power MOSFETs under the off-state. The results show that the body diodes of planar and trench devices with a shallow P+ depth are highly reliable, while those of the trench devices with the deep P+ implantation exhibit significant degradation. In conclusion, the body diode degradation in trench devices is mainly influenced by P+ implantation-induced BPDs. Therefore, a trade-off design by controlling the implantation depth/dose and maximizing the device performance is crucial. Moreover, the deep JFET design is confirmed to further improve the body diode reliability in planar devices.

AC-Stress Degradation in SiC MOSFETs

This work presents very recent results regarding threshold-voltage (VT) degradation due to the application of an AC gate-bias stress (also known as a gate-switching stress). We show that this phenomenon includes both a seemingly-permanent VT shift and an increase in the observed VT hysteresis. This degradation effect is found primarily in trench-geometry devices when exposed to what can be described as a negative bias overstress that exceeds the negative bias rating of the device, but that not all trench devices are equally susceptible, suggesting that device design and processing details are critical in limiting the severity of this effect.

Suppression of Short Channel Effects for a SiC MOSFET Based on the S-MOS Cell Concept

This paper investigates the short channel effects (SCE) of the recently proposed Singular Point Source MOS (S-MOS) SiC MOSFET. The study was carried out using 2D and 3D TCAD simulations for a planar, trench and S-MOS 1200V SiC MOSFETs for the IV output characteristics up to 1200V and under short circuit transient conditions. The S-MOS device shows no SCE up to the rated voltage when compared to reference planar and trench devices which exhibit strong SCE. This is due to the appropriate P++ protection of the N++ source and the electric field shielding due to the narrow mesa dimensions between orthogonal trenches where the channel is located.

Design and Analysis of Walking device of Multi-function Ecological Planting Grass Cart

Aiming at the problems of complex structure and difficult control of the walking device of the grass planting cart, a walking device of the ecological grass planting cart was designed, including the frame, walking wheel, profile device, depth limiting device, etc. The device limits the depth of three blocks and simulates the shape of the working ground. From the perspective of the soil contact force field and displacement field, EDEM software was used to simulate the discrete elements of the driving wheel and soil suppression effect. It can be seen from the analysis results that the driving wheel has a good suppression effect on soil particles. The depth-limiting effect of the walking device is simulated, and the results show that the distribution area and depth of the contact force field between the three-gear trench device and soil particles are different, and the depth-limiting effect is good.

(Invited) Updated Issues Regarding Threshold-Voltage Instability in SiC MOSFETs

This work will provide an updated overview of our understanding of several key reliability issues for SiC power MOSFETs related to threshold-voltage stability. Threshold-voltage instability likely occurs due to the charging and discharging of near-interfacial oxide traps in response to a change in gate bias. If enough traps change charge state, it can lead to significant shifts in the threshold voltage, which may in turn lead to increases in leakage current in the off state, or increases in on-state resistance in the on state. An important question is, what is the best—or most appropriate—test method to use to determine the reliability of these devices. It has recently been observed that one commercial device manufacturer has quite large instabilities, even in previously unstressed devices, and that such large instabilities can result in significant increases in on-resistance during normal switching conditions, thereby degrading circuit performance. Other issues addressed will be the effects of AC Stressing, measuring both static and dynamic threshold voltage, and comparing effects in trench and planar geometry devices.

Investigation on the Degradations of Parallel-Connected 4H-SiC MOSFETs Under Repetitive UIS Stresses

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications.

Enhanced Transient Behavior in MIS(p) Tunnel Diodes by Trench Forming at the Gate Edge

In this article, a new type of metal-insulator-semiconductor (MIS) tunnel diode (TD), trench MIS TD, was investigated. From the current-voltage characteristics, memory retention, and memory endurance measurements, we found that the trench MIS TDs not only have lower reverse bias current, but also show stronger transient current compared to traditional planar structure MIS TDs. For example, in the 1000-cycle memory endurance test, we observed a 25 times larger current window (CW) in trench devices than the CW of planar devices. We attribute the lower reverse bias current to the fewer minority carriers (electrons) in trench MIS TDs, which is supported by the high-frequency capacitance-voltage (C-V) measurement. As for the enhanced transient behavior of trench MIS TDs, we proposed a mechanism based on the understanding of fewer minority carriers in trench devices to explain our observation. Eventually, we examined the effect of different equivalent oxide thicknesses (EOTs) on the CW and found that the trench devices have better CW in a wide EOT range. Because of the enhanced transient behavior leading to better memory CW, trench MIS TDs have the potential to serve as memory devices.

(Invited) Updated Key Issues for SiC MOSFET Reliability

This work will provide an updated overview of our understanding of several key reliability issues for SiC power MOSFETs, including threshold-voltage stability, body-diode robustness, and short-circuit current robustness. We will also discuss recent results regarding the modeling of high-field breakdown in SiC and other power semiconductor devices.Threshold-voltage instability likely occurs due to the charging and discharging of near-interfacial oxide traps in response to a change in gate bias. If enough traps change charge state, it can lead to significant shifts in the threshold voltage, which may in turn lead to increases in leakage current in the off state, or increases in on-state resistance in the on state. An important question is, what is the best—or most appropriate—test method to use to determine the reliability of these devices. A key factor is the measurement speed used to determine the magnitude of the threshold-voltage instability. It has recently been observed that one commercial device manufacturer has large instabilities, even in previously unstressed devices, and that such large instabilities can result in significant increases in on-resistance during normal switching conditions, thereby degrading circuit performance.Some suppliers of SiC power MOSFETs are producing devices with low basal plane dislocation (BPD) density, resulting in decreased bipolar degradation during normal operation of its integral body-diode. However, not all suppliers manage their BPD densities to the same degree, resulting in a variation in responses observed across suppliers. Even devices from a single supplier with the same date code exhibited varying levels of degradation for identical body-diode stress and measurement conditions. Unlike other extended defects, BPDs when faulted, leads to degradation in both the body-diode and MOSFET characteristics. These faulted BPDs induce stacking faults that expand over time and limits the reliability of some commercially available SiC MOSFETs. This degradation phenomenon necessitates the development of an appropriate reliability test standard for SiC to separate good devices from bad ones. Three of the five major suppliers of 1200-V SiC MOSFETs showed varying levels of bipolar degradation in both their body-diode forward voltages and their MOSFET on-resistances. Two out of three suppliers of 1700-V SiC MOSFETs showed significant bipolar degradation issues with one particular supplier’s devices showing forward voltage changes of 1.3 V to 2.5 V from their pre-stress values. Their on-state resistance values were also significantly degraded.Another important aspect of SiC MOSFET reliability is its robustness to short-circuit current conditions that can occur in many power electronics applications utilizing a half-bridge topology. Since both planar and trench device architectures are commercially available, electrical results have been generated to highlight their short-circuit capabilities under similar circuit conditions. Our electrical results show that trench devices have lower robustness in comparison to planar devices of similar ratings. These differences in short-circuit withstand times can be attributed to the smaller heat conduction volume of the trench design coupled with its higher saturation drain current for the same gate-drive voltage. The existing test method for short-circuit withstand time in the MIL-STD may overestimate the actual withstand time because it relies on a single gate-pulse method. Electrical results indicate that an incremental gate-pulse method may be more accurate in determining the actual withstand time, and it has proven to be more effective in determining latent failures missed by the standard method.Another key issue for power devices in general is the trade-off between on-state resistance and blocking voltage. One of the key advantages of wide bandgap (WBG) materials such as SiC is that it can block the same voltage as Si using a much thinner, and more highly-doped, blocking layer. This results in a much lower on-state resistance at the same rated voltage. The superior high-field properties of WBG (and ultra WBG) power semiconductor materials also enable them to block much higher voltages than Si is able—as long as the background doping is low enough. We will present recent work, using impact ionization coefficients from the literature, to calculate avalanche breakdown as a function of epi-layer thickness and doping, thereby determining on-state resistance versus breakdown voltage for SiC and GaN. We will compare these results to Si, as well as to UWBG materials such as diamond, AlGaN, and Ga2O3. It is observed that SiC and GaN have very similar characteristics in terms of critical field, and in their relationships between on-state resistance and blocking voltage.

(Invited) Selected Issues for SiC Mosfet Reliability

There remain a number of potential reliability issues associated with SiC power MOSFETs that interest the reliability standards community, of which this work will provide an overview of our understanding of three of those issues: (1) threshold-voltage stability; (2) body-diode robustness; and (3) short-circuit current robustness. A recent survey of commercially-available devices shows a wide range of responses in threshold-voltage stability, which is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct-tunneling mechanism in response to changes in gate bias, necessitating the need for faster measurements and the maintenance of the stress bias before making post-stress measurements. The observation of the activation of additional traps during bias-temperature stress in older devices underlines the need for additional attention to high-temperature charging effects as well. It is the case for at least one commercial vendor, that improvement in lower BPD density and enhanced device fabrication have led to significant improvements in body-diode robustness. Earlier vintage devices had showed varying levels of degradation in both the body diode and MOSFET on-state properties following current stress of the body diode, as well as degradation in the off-state drain leakage current. Experimental results show that both commercially-available planar and trench SiC MOSFETs have suitable short-circuit (SC) withstand times, ranging from 6 to 13 μs at T = 25 °C, VGS = 20 V, and VDS = 600 V. Even when trench devices have an identical rating to planar devices, they likely will have a significantly smaller area and heat conducting volume, contributing to their lower robustness for the same SC test conditions. All the electrical results reported seem to be consistent with thermally-driven failure mechanisms. The official standard test method of a single, long pulse is found to not be as effective as a series of shorter, incremental gate pulses, which more accurately detect failure time, even in the case of latent or delayed failure. All this work will be presented within the context of standards development within JEDEC, including a number of SiC-focused reliability task groups.

Detection and Cryogenic Characterization of Defects at the SiO2/4H-SiC Interface in Trench MOSFET

We employed the thermal dielectric relaxation current (TDRC) method for the detection and cryogenic characterization of traps at the 4H-SiC/SiO2 interface in n-channel trench MOSFETs and n-MOS trench capacitors. The interface of trench devices on the ( $\textsf {11}\overline {2}\textsf {0}$ )-plane atomically differs from the interface of standard lateral devices [(0001)-plane]. In the MOSFET, two TDRC signal peaks originating from electron traps were found and characterized by parameter variation in TDRC measurements. One peak corresponds to interface states located 0.13 eV below the 4H-SiC conduction band edge EC. The other one is attributed to the near-interface traps (NITs) with an electron emission barrier of 0.3 eV. The NIT peak shows an inverse dependence on the discharging voltage compared to regular interface states. In contrast to the MOSFET, only NITs were measured in n-type MOS capacitors. The results found in trench devices were also confirmed for lateral devices. Therefore, we show that the study of SiC MOS capacitors is not sufficient for the understanding of degradation mechanisms in SiC MOSFETs. The interface states at EC-0.13 eV detected in MOSFETs are assumed to contribute to the degradation of the apparent channel mobility and ON-resistance of SiC MOSFETs. These states are strongly reduced by annealing in NO compared to N2.

Buried-Heterostructure Quantum Cascade Lasers Fabricated Using a Sacrificial Layer and a Two-Step Regrowth Process

In recent years, the technology of the quantum cascade laser (QCL) has drastically improved, as proven by room temperature continuous wave (CW) operation, high optical power, low dissipation devices, and accessible spectral range [1]. As a result, QCLs have drawn a great deal of interest for their various applications in trace-gas sensing, defense countermeasures, spectroscopy and free-space communications [2]. The performance of QCLs is primarily dependent on the design of the active region, usually gown by MBE (molecular beam epitaxy). Nevertheless, the laser performance are also influenced by the thermal properties and optical losses introduced by the fabrication technology, in particular in continuous-wave operation. In that respect, the buried heterostructure (BH) approach, which is a standard and reliable telecommunications laser manufacturing technique, offers unique possibilities to achieve effective thermal dissipation and lateral single modes. In standard BH designs, the process starts by the definition and etching of the ridge mesa using a dielectric mask. The latter (SiO2 or SiN) is also used as the masking material for the selective regrowth by metal-organic vapor phase epitaxy (MOVPE) of a thick insulating InP (Fe) layer over the entire laser structures. Unfortunately, the selective regrowth of InP:Fe is not a trivial process. Indeed, it is extremely difficult to achieve an ideal planarized regrowth, i.e, completely burying the laser ridge, while maintaining a planar surface. In addition to growth conditions, the characteristics of the regrown InP layer strongly depend on the sidewall profile of the ridges, as well as on the physical parameters of the dielectric mask (thickness, width…) [3]. The complexity of the etching and regrowth process further increases for thick layer structures, such as for long wave QCLs, whose ridges can be >10 µm deep. In effect, deep ridge etching generates big undercuts in the structures and consequently, highly non uniform active region widths. Moreover, the thick selective regrowth step, needed for planarization, tends to favor the appearance of crystal growth artifacts (crystallites, voids, “rabbit ears”…) in the vicinity of the ridges, which deteriorate the performance of the regrown structures. In some cases, additional photolithographic and back-etching steps might even be required to improve the planarity of the structure. Another method that allows overcoming the aforementioned limitations is to use a modified buried heterostructure concept, with two MOVPE regrowth steps [4]. In this case, the waveguide pattering and etching is constituted only by the active layers (<3 μm). Hence, the active region is laterally insulated and planarized using selective growth of a much thinner InP:Fe layer. The dielectric layer is subsequently removed and the optical cladding is grown over all the structure. An additional advantage of a thinner regrowth is the reduced amount of defects due to the selective growth of InP:Fe. However, the undercut formed by the overhanging dielectric mask (needed for the selective growth in first MOVPE step), and the tapered profile of the active region can result in a reduced material thickness close to the upper edges of the active region. In this case, the material thickness can be too thin and induce carrier tunneling through the interface between the active region and the lateral regrowth (insufficient electrical isolation). In this perspective, we report an optimized BH-QCL approach obtained by adding an InP layer and a sacrificial InGaAs cap layer on top of the MBE grown active region. As shown in the attached figures (FIB/SEM cross-section profiles), the lateral thickness of the insulating and planar regrowth is increased and reduces potential leakage paths. Using this approach, BH QCL regrowths were successfully carried out with reproducible and good epitaxial growth quality (smooth and uniform regrown layers, planar surfaces, no “rabbit-ears” and defect free interfaces) around the etched ridges, permitting the fabrication of BH-QCLs with good beam quality and hundreds of mW of optical power at room temperature. The growth and optimization of the BH process, as well as the fabrication and testing of the laser devices will be presented and compared to conventional double trench devices.

Isotropic Oxidation by Plasma Oxidation and Investigation of RIE Induced Effects for Development of 4H-SiC Trench MOSFETs

In this work, we examined the oxidation growth rates of the (0001) Si-face and (11−20) a-faces of 4H-SiC by carrying out oxidation in the 850°C-950 °C temperature range in a plasma afterglow furnace for application to trench MOSFETs. At 900 °C, this method results in almost equal oxide thickness on the Si-face and a-face which would nominally correspond to trench bottom and sidewalls in trench devices. Our results indicate that after NO annealing, the electronic properties of the plasma oxidized SiO2/SiC interface is comparable to control samples with gate oxides formed by dry oxidation at 1150 °C followed by NO annealing. Next, the effect of reactive ion etching (RIE) of 4H-SiC surfaces prior to gate oxidation was investigated using planar 4H-SiC MOS capacitors. Our experiments show that oxidation followed by NO annealing of surfaces with smooth morphology following the RIE step, results in similar interface charge and trap densities as MOS capacitors which did not undergo the RIE etching.

Short-Circuit Robustness of SiC Trench MOSFETs

An investigation into the robustness of 1200-V/80-mΩ commercial trench-gate MOSFETs reveals that the critical energy for failure during short-circuit operation is reached in shorter times in comparison to similarly rated planar DMOSFETs under similar stress conditions. This critical energy for trench devices was estimated to be between 615 mJ to 660 mJ depending on the gate-drive voltage. These values are considerably smaller when compared to DMOSFETs from the same manufacturer. In comparison to planar designs, trench devices can have lower losses, and manufactured with much smaller chip size for the same device rating. As a result, higher power density, improved efficiency, lower chip costs, and higher yields for trench designs are possible, but these enhancements are offset by a reduction in short-circuit capability. The critical short-circuit time for a 600-V bus voltage is shown to be dependent on gate-drive voltage magnitude, with higher gate voltages leading to increased peak short-circuit current, higher power dissipation, and reduced short-circuit capability.

Effect of Negative Gate Bias on Single Pulse Avalanche Ruggedness of 1.2 kV Silicon Carbide MOSFETs

When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at VGS = -10 V did not result in improvements in ruggedness.

Planar to Trench: Short Circuit Capability Analysis of 1.2 kV SiC MOSFETs

This paper presents an insight into the short circuit (SC) capability of Rohm’s discrete 1.2 kV, 80 mΩ state-of-the-art silicon carbide (SiC) double trench metal-oxide-semiconductor field effect transistor (MOSFET). SC measurements are performed to compare the behavior of Wolfspeed’s similarly rated 1.2 kV, 80 mΩ planar MOSFET with the Rohm trench devices. Short circuit withstand time (SCWT) of both designs under nominal operating conditions at room temperature is measured by performing destructive SC tests.

Supercurrent in Graphene Josephson Junctions with Narrow Trenches in the Quantum Hall Regime

ABSTRACTCoupling superconductors to quantum Hall edge states is the subject of intense investigation as part of the ongoing search for non-abelian excitations. Our group has previously observed supercurrents of hundreds of picoamperes in graphene Josephson junctions in the quantum Hall regime. One of the explanations of this phenomenon involves the coupling of an electron edge state on one side of the junction to a hole edge state on the opposite side. In our previous samples, these states are separated by several microns. Here, a narrow trench perpendicular to the contacts creates counterpropagating quantum Hall edge channels tens of nanometres from each other. Transport measurements demonstrate a change in the low-field Fraunhofer interference pattern for trench devices and show a supercurrent in both trench and reference junctions in the quantum Hall regime. The trench junctions show no enhancement of quantum Hall supercurrent and an unexpected supercurrent periodicity with applied field, suggesting the need for further optimization of device parameters.

Characterization and Comparison of Planar and Trench Silicon Carbide (SiC) Power MOSFETs

This paper presents a comprehensive evaluation and experimental comparison of silicon carbide power MOSFETs through double pulse test. First, a universal hardware platform is designed and developed to test power semiconductor devices with various device packages and measuring requirements. Using the developed platform, the static characteristics and switching performance of the two types of SiC MOSFETs (one planar and one trench type) are evaluated under different case temperatures from 25 oC to 175 oC. Based on the evaluation data, a comparison of both SiC MOSFETs is conducted in terms of their on-state resistance, switching loss, and temperature dependent behavior. It is found that the latest trench SiC MOSFETs present similar switching loss while much lower conduction loss compared to existing commercial planar SiC MOSFETs. Moreover, the trench devices show a nearly temperature independent switching loss, which is beneficial to suppress the potential thermal runaway issue under high temperature continuous operation.

Characterization and Comparison of Planar and Trench Silicon Carbide (SiC) Power MOSFETs

This paper presents a comprehensive evaluation and experimental comparison of silicon carbide power MOSFETs through double pulse test. First, a universal hardware platform is designed and developed to test power semiconductor devices with various device packages and measuring requirements. Using the developed platform, the static characteristics and switching performance of the two types of SiC MOSFETs (one planar and one trench type) are evaluated under different case temperatures from 25 oC to 175 oC. Based on the evaluation data, a comparison of both SiC MOSFETs is conducted in terms of their on-state resistance, switching loss, and temperature dependent behavior. It is found that the latest trench SiC MOSFETs present similar switching loss while much lower conduction loss compared to existing commercial planar SiC MOSFETs. Moreover, the trench devices show a nearly temperature independent switching loss, which is beneficial to suppress the potential thermal runaway issue under high temperature continuous operation.

High aspect ratio iridescent three-dimensional metal–insulator–metal capacitors using atomic layer deposition

The authors report on the structural and electrical properties of TiN/Al2O3/TiN metal–insulator–metal (MIM) capacitor structures in submicron three-dimensional (3D) trench geometries with an aspect ratio of ∼30. A simplified process route was employed where the three layers for the MIM stack were deposited using atomic layer deposition (ALD) in a single run at a process temperature of 250 °C. The TiN top and bottom electrodes were deposited via plasma-enhanced ALD using a tetrakis(dimethylamino)titanium precursor. 3D trench devices yielded capacitance densities of 36 fF/μm2 and quality factors &amp;gt;65 at low frequency (200 Hz), with low leakage current densities (&amp;lt;3 nA/cm2 at 1 V). These devices also show strong optical iridescence which, when combined with the covert embedded capacitance, show potential for system in package (SiP) anticounterfeiting applications.