Trench Corners Research Articles

Understanding Short-Circuit Failure Mechanism of Double-Trench SiC Power MOSFETs

The short-circuit (SC) failure mechanism of double-trench silicon carbide (SiC) power metal-oxide- semiconductor field-effect transistors (MOSFETs) is comprehensively studied and analyzed. Unlike traditional planar-gate devices which die from thermal runaway, the double-trench ones exhibit a different SC failure phenomenon. After enduring an ultimate SC stress cycle, the gate of the double-trench device breaks down while the conducting and blocking characteristics of the body diode remain stable. During the SC process, a substantial negative gate current from the semiconductor side to the poly gate side is observed. Silvaco TCAD simulations demonstrate that ultrahigh current density and impact ionization appear at the gate trench corners simultaneously, driving the generated hot holes through the oxide, forming the negative gate current. The sustained action of this gate current component on the oxide finally results in the failure. Moreover, the influence that bias voltages have on the SC endurance capability of the device is analyzed. In general, the higher the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> are the shorter the SC endurance time will be. It is also found that the double-trench device fails with a higher junction temperature when stressed under a lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> condition, implying that the temperature rarely affects the failure, proving the correctness of the proposed SC failure mechanism.

Verification of Single-Pulse Avalanche Failure Mechanism for Double-Trench SiC Power MOSFETs

The failure mechanism of double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under single-pulse avalanche stress is verified. Instead of the widely reported burning out failure mechanism for planar-gate devices, double-trench SiC power MOSFETs suffer from a totally different failure mechanism, as they can only endure a much lower maximum single-pulse avalanche energy (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">as</sub> ). It is found that during the avalanche process, obvious gate leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) appears, which is resulted from the high impact ionization rate and high electric field along the gate trench bottom oxide interface, especially the trench corners. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> continuously grows along with the increase in the peak load current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> peak</sub> ), eventually leading to the breakdown of the trench bottom gate oxide under avalanche status. By increasing the value of gate resistor (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> raises the gate-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> gs</sub> ) during the avalanche process, forcing the channel region in an inversion state. Part of the avalanche current is then diverted into the forward conductive current, changing the failure mode from breakdown of the gate oxide to burning out of the entire device. Moreover, the influence of different avalanche stress conditions, including the di/dt and the ambient temperature (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> ), on the single-pulse avalanche endurance capability of double-trench SiC power MOSFETs is investigated. All the samples express a similar failure phenomenon. The higher the di/dt is, the shorter the avalanche time the device can endure. This is because the higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> results in a higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> during the avalanche process, leading to early failure of the gate oxide. However, the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">a</sub> rarely influences the E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> as</sub> of the device, indicating that the single-pulse avalanche-induced failure of double-trench SiC power MOSFETs has little business with the melting of the lattice or package, demonstrating the correctness of the failure mechanism proposed in this article.

Effects of strain energy on the recrystallization within narrow metallization

Elastic strain energy within materials due to recrystallization of grains with a specific orientation, or texture, can be calculated through the use of Eshelby inclusions, where a recrystallized grain can be treated as an elastically anisotropic inclusion in an elastically isotropic matrix. The evolution of texture that minimizes elastic strain energy is shown to be dependent on the specific strain state. The interaction strains generated by this elastic incompatibility and corresponding strain energy have been derived for grains with cubic symmetry for general forms of the applied strain tensor. For uniaxial and isotropic, biaxial strain tensors, the interaction strain tensor and corresponding elastic strain energy density are proportional to the orientation parameter, Γ, which relates the Miller indices of the recrystallized grain to the loading direction: either parallel to the uniaxial strain direction or perpendicular to the plane in which isotropic biaxial strain is applied. It is rigorously proven that for elastically isotropic inclusions, corresponding to Γ = 1/5, the interaction strain is zero. Although blanket films often possess an isotropic, biaxial stress state, metallization trenches can exhibit a combination of normal and shear strain components, particularly near the trench corners. It is shown that in cases where shear is present, the resulting elastic strain energy can be lowered by the development of (110) texture despite its higher surface energy, as has been observed in thin films and interconnect trenches. These results suggest that shear strain can play an important role in the evolution of texture in narrow, metallization structures.

An Improvement of Trench Profile of 4H-SiC Trench MOS Barrier Schottky (TMBS) Rectifier

A 4H-SiC TMBS diode with improved trench corners has been demonstrated. The trench profiles are improved by using 12sccm/28sccm of SF6/Ar mixture, and a working pressure of 12 mtorr for RIE etching. The depth of micro-trenching has been reduced to lower than 0.07 μm. The 4H-SiC TMBS diode with improved trench profiles shows a breakdown voltage over 725V.

A novel trench gate MOSFET with a multiple-layered gate oxide for high-reliability operation

Gate dielectrics in trench structures for trench gate metal oxide semiconductor field-effect transistor (MOSFET) power devices are very important to realize excellent characteristics. In this paper we describe multiple-layer gate dielectrics for trench gate MOSFETs with both thermal and chemical vapor deposition (CVD) gate oxides that exhibit excellent gate oxide properties and surface roughness. Through various trench etching experiments for better surface conditions in the trench, the optimum etching gas chemistry and etch conditions were found. The destruction of gate dielectric in trench gate MOSFET occurs at the top and the bottom trench corner edges. The structure of the gate electrode is pulled out with the polysilicon layer which is buried in the trench. Thus, high electric field operation is inevitable at the gate between source diffusion and the gate polysilicon. Moreover, the trench corner oxide suffers from the high electric field. We propose a multiple-gate dielectric structure of a thermal oxide and CVD oxide for highly reliable operation of the device. This enables trench surface smoothing and low thermal stress at the trench corners and provides the oxide thickness uniformity, giving superior device characteristics of high breakdown voltage and low leakage current. These improvements are caused by the excellent quality of the gate oxide and the good thickness uniformity that is formed at the inner trench with a specific geometrical factor.

Shape Control and Roughness Reduction of SiC Trenches by High-Temperature Annealing

The high-temperature annealing of SiC trenches has been investigated for improving the shape of trenches and the smoothness of trench sidewalls. In a SiH4-added Ar (SiH4/Ar) atmosphere, the transformation of SiC trenches required a pressure of 80 Torr and a temperature of 1700 °C; The inner surface of the trenches became smoother without significant etching, while the sample surface became rougher. From the time dependence of the curvature at the trench upper corner, the authors consider that both surface diffusion and evaporation–condensation contribute to the transformation, as opposed to the annealing in H2 reported by another group where transformation is driven mainly by evaporation–condensation. The present authors did not observe a significant change in trench shape in a H2 atmosphere at annealing temperatures up to 1400 °C, except for a smoothening of sample surfaces. The proposed two-step annealing process, consisting of annealing at 1700 °C in SiH4/Ar followed by annealing at 1400 °C in H2, realized rounded trench corners and smooth surfaces simultaneously without significant etching.

Surface Generation-Recombination Processes of Gate and STI Oxide Interfaces Responsible For Junction Leakage on SOI

Carrier generation-recombination at the top, corner and trench surfaces of silicon-on-insulator (SOI) diode bodies have been studied using the standard gated-diode methodology and new test structures with independent trench-side gates. The influences of top or trench gate voltage, temperature and junction bias have been elucidated. Four distinct diode current peaks are observed during top-gate voltage sweeps. Qualitative analysis has assigned these peaks to surface recombination at the different surface areas of SOI bodies. The coexistence of multiple recombination current peaks might be related to silicon faceting at top trench corners. During top-gate voltage sweeps, STI-gate voltage causes a larger recombination current peak shift for interface traps at the SOI trench corners and walls than those at top SOI interface. A new model involving an oxide trap within the STI oxide has been proposed to interpret the random telegraphic signal (RTS) noise of a gated-diode at high carrier injection and temperature.

Void generation during the annealing process of very narrow copper wires

We carried out experiments on stress-induced void formation in ultrathin Cu wires while varying heat-treatment temperature, wire dimensions, and overlayer thickness. We also did molecular dynamics simulations of void formation in a buried wire of nanometer scale and compared these results with experimental results to clarify details of the void formation mechanism. The experimental and simulation results showed good accordance in explaining the effects of wire width, overlayer thickness, and cooling rate on void formation. (1) The narrower the wire width, the easier the void formation. (2) The thicker the overlayer, the easier the void formation. (3) The larger the cooling rate, the greater the suppression of void formation. From the obtained results, we constructed a void formation model for a buried wire. The basic concept of the model describes how local strain at four trench corners is relaxed in the buried wire in the annealing process. There are two ways to relax the local strain: (1) structural relaxation to strengthen adhesion between the wire and substrate and (2) reduction of the surface area to minimize surface energy. The way preferred is dependent on how parameters such as system temperature and wire dimensions are combined. Based on the void formation model, we interpreted the effects of wire strain, wire dimensions, and overlayer thickness.

Shape Transformation of 4H-SiC Microtrenches by Hydrogen Annealing

This study investigates the shape transformation of 4H-SiC microtrenches that occurs during high-temperature hydrogen annealing, which is used to improve growth on such prepared substrates. The trenches have micron-sized widths and depths and were annealed in hydrogen ambient at temperatures of 1400–1600 °C for 30–3600 s. After hydrogen annealing, cross-sectional images of the samples were obtained by scanning electron microscopy (SEM). These SEM images reveal that the top and bottom trench corners become rounded during hydrogen annealing. The top trench corners become rounded by an etching reaction, whereas the bottom trench corners become rounded as a result of a regrowth phenomenon that involves the transportation of atoms. This study analyzes the mechanism of these transformations in terms of Mullins' continuum model. The results suggest that the evaporation–condensation process is dominant in the case of SiC annealing.

Micro-patterning of NdFeB and SmCo magnet films for integration into micro-electro-mechanical-systems

The integration of high-performance RE-TM (NdFeB and SmCo) hard magnetic films into micro-electro-mechanical-systems (MEMS) requires their patterning at the micron scale. In this paper we report on the applicability of standard micro-fabrication steps (film deposition onto topographically patterned substrates, wet etching and planarization) to the patterning of 5–8 μm thick RE-TM films. While NdFeB comprehensively fills micron-scaled trenches in patterned substrates, SmCo deposits are characterized by poor filling of the trench corners, which poses a problem for further processing by planarization. The magnetic hysteresis loops of both the NdFeB and SmCo patterned films are comparable to those of non-patterned films prepared under the same deposition/annealing conditions. A micron-scaled multipole magnetic field pattern is directly produced by the unidirectional magnetization of the patterned films. NdFeB and SmCo show similar behavior when wet etched in an amorphous state: etch rates of approximately 1.25 μm/min and vertical side walls which may be attributed to a large lateral over-etch of typically 20 μm. Chemical–mechanical-planarization (CMP) produced material removal rates of 0.5–3 μm/min for amorphous NdFeB. Ar ion etching of such films followed by the deposition of a Ta layer prior to film crystallization prevented degradation in magnetic properties compared to non-patterned films.

고 전력 DMOSFET 응용을 위한 트렌치 게이트 형성에 관한 연구

In this study, the etched trench properties including cross-sectional profile, surface roughness, and crystalline defects were investigated depending on the various silicon etching and additive gases, For the case of HBr<TEX>$He-O_2SiF_4$</TEX> trench etching gas mixtures, the excellent trench profile and minimum defects in the silicon trench were achieved. Due to the residual oxide film grown by the additive oxygen gas, which acts as a protective layer during trench etching, the undercut and defects generation in the trench were suppressed. To improve the electrical characteristics of trench gate, the hydrogen annealing process after trench etching was also adopted. Through the hydrogen annealing, the trench corners might be rounded by the silicon atomic migration at the trench corners having high potential. The rounded trench corner can afford to reduce the gate electric field and grow a uniform gate oxide. As a result, dielectric strength and TDDB characteristics of the hydrogen annealed trench gate oxide were remarkably increased compared to the non-hydrogen annealed one.

Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array beyond 90nm CMOS Technology

ABSTRACTExperimental characterization of nanocrystal formation in gate trenches were performed, which includes the analyses of number fluctuation, the size distribution, and the correlation of the size and number density in gate patterns with various feature sizes from 50nm to 150nm. The gate regions with 51nm oxide wall are defined by e-beam lithography and reactive ion etching (RIE). By using direct-deposit self-assembly (i.e., evaporation and post-annealing), Au, Ag, and Pt nanocrystals are formed on the gate tunneling oxide. From the statistical evaluation by scanning electron microscopy (SEM) observation, the number fluctuation of nanocrystals in a gate trench could be always controlled under 12%, while it follows the Poisson distribution in the unconstrained self-assembly. This is mainly due to the confinement effect by the trench sidewalls, corners, and edges. The current study demonstrated that the direct-deposit self-assembly process could be successfully adapted beyond 90nm metal nanocrystal memory technology with satisfactory parametric yield in the nanocrystal number density.

Behavior of trench surface by H 2 annealing for reliable trench gate oxide

A new technique for highly controllable trench corner rounding (TCR) at top and bottom of the trench using pull-back and hydrogen annealing has been developed and investigated. The pull-back process combined with hydrogen annealing can control the TCR radius at the top corners of the trench. The silicon migration generated by hydrogen annealing at the trench corners provides (1 1 1) and (3 1 1) crystal planes and gives a uniform gate-oxide thickness, resulting in highly reliable trench gate DMOSFETs with high breakdown voltages and low leakage currents. The gate breakdown voltage of a trench DMOSFET fabricated by using hydrogen annealing was 27 V, which was 22% higher than that of no hydrogen-annealed devices. The on-resistance of the trench gate DMOSFET fabricated by using the trench cell of 45,000 is about 55 mΩ at a gate voltage of 10 V under a drain current of 5 A.

Influence of interface relaxation on passivation kinetics in H2 of coordination Pb defects at the (111)Si/SiO2 interface revealed by electron spin resonance

Electron spin resonance studies have been carried out on the isothermal passivation kinetics in 1 atm molecular H2 of trivalent Si traps (Pbs;Si3≡Si•) at the interface of thermal (111)/Si/SiO2 as a function of oxidation temperature Tox in the range 250–1100 °C. Interpretation within the generalized simple thermal (GST) passivation model, based on first-order interaction kinetics, reveals a distinct increase in spread σEf in the activation energy for passivation Ef with decreasing Tox (∼3 times in the covered Tox window), while the other key kinetic parameters (Ef, preexponential factor) remain essentially unchanged. The variation in σEf is ascribed to differently relaxed interfacial stress, affecting the spread in Pb defect morphology. In a second analytic part, the impact of the variation in Ef, and correlatively in the activation energy Ed for PbH dissociation, on Pb–hydrogen interaction kinetics is assessed within the GST-based full interaction scheme, describing parallel competing action of passivation and dissociation. In particular, the passivation behavior in 1 atm H2 of an initially exhaustively depassivated Pb system, is analyzed exposing, as a major result, that growing spreads σEf, σEd result in a drastic reduction in passivation efficiency (drop by four orders of magnitude for a threefold increase in σEf). For σEf/Ef≳20%, the Pb system cannot be inactivated beyond the 90% level, incompatible with device quality requirements. Heating time/temperature vs spread conditions for optimum passivation in H2 have been established, and the technological impact of altering σEf, σEd is discussed. At film edges and trench corners, which are vulnerable local regions of exces stress, and hence enhanced σEf, σEd, an edge defeat effect with respect to passivation is exposed. Within the relentless scaling of Si-based integrated circuit devices, the growing relative impact of edge regions may jeopardize proper passivation of interface traps in the conventional way in future device generations.

A numerical comparison between MOS control and junction control high voltage devices in SiC technology

A comprehensive numerical comparison between MOS control (MOSFETs) and junction control (JFETs) devices in SiC technology is presented. The study is carried out using the MEDICI device simulator and covers an interval of blocking voltages ranging from 600 V to 6.5 kV. The gate oxide failure phenomenon in SiC trench MOSFETs is studied and the effect of wide trenches and rounded trench corners on the voltage blocking performance is investigated. The paper continues with a comparative study of SiC MOSFETs and SiC JFETs. The JFET chosen has a particular channel geometry featuring a highly doped buffer layer to reduce the on-state resistance. The influence of the buffer layer and the gate voltage on the JFET on-state/breakdown performance is carefully investigated. The study concludes with a mixed-mode simulation of the transient behaviour of a 1.2 kV SiC JFET–Silicon MOSFET pair in a CASCODE configuration as a viable alternative to a single switch (either SiC MOSFET or JFET).

Formation of Slit-Like Voids at Trench Corners of Damascene Cu Interconnects

Stress voiding was investigated in damascene Cu lines embedded in Ta/TaN/SiO2/Si. Microstructure was observed before and after heat treatment at 723 K using a focused ion beam (FIB) technique. The distribution of thermal stress was calculated using a three-dimensional finite element method (FEM). FIB observation revealed that slit-like voids were formed at trench shoulders both before and after heat treatment. FEM calculation indicated that a large shear stress concentration occurred at the voided sites. The coincidence between the FIB observation and the FEM calculation suggests that the slit-like voids were formed by shear-mode delamination of Cu from the Ta/TaN barrier layer.

Misfortune, challenge, and success: defects in processed semiconductor devices

Process-induced defects are still a key issue in semiconductor device production. The increasing miniaturization and number of process steps as well as the introduction of new materials and processes make the understanding of defect generation more complex. In this paper, we describe small defects in silicon, such as dry etching damage, implantation mask defects, and silicidation defects, which may be considered as nuclei for secondary defect formation. In two examples, transmission electron microscopy and stress simulation are applied to study source-drain transistor leakage and dislocation formation at trench corners in silicon.

The dependence ofUMOSFET characteristics and reliability on geometry andprocessing

We have examined the impact of trench processing and trench anddevice cell geometries on the characteristics of a singlen-channel U-shaped trench metal-oxide-silicon field-effecttransistor (n-UMOSFET) and a device cell comprising severaln-UMOSFETs. The geometrical parameters investigated includedthe trench depth and width, the trench cross-section and thedevice cell pitch. We have found out that the geometry does notaffect the electron mobility in the channel; however, theeffects of the geometry on the characteristics of the isolateddevice or device cell are manifested on the spreading resistance of thedrain end. Trench processing, in the form of trench etching,trench cleaning and subsequent gate-oxide growth, is observed toprimarily influence the n-UMOSFET's immunity to electricalstress, which is studied using charge pumping current andgate-oxide breakdown measurements. It is shown that thegate-oxide edge adjacent to the drain and the oxide/siliconinterface overlapping the drain are the regions most susceptibleto degradation by Fowler-Nordheim stress. Theseobservations coupled with results from scanning electronmicroscopy suggest that the gate-oxide growth non-uniformity aswell as its condition at the trench corners are the key factorsin determining the n-UMOSFET's reliability.

Influence of the trench corner design on edge termination of UMOS power devices

In this article, the voltage blocking capability of UMOS power devices is experimentally demonstrated to be limited by the onset of a premature breakdown at the corners of the trench located at the device periphery. With the aid of numerical simulations performed in cylindrical co-ordinates, it is shown for the first time that a race-track shape of the trench gate fingers alleviates the electric fields at the trench corners and maximizes the UMOS voltage blocking capability. In addition, it is also shown that the breakdown voltage at the trench corners can be made to exceed the UMOS unit cell breakdown voltage by using a deep p diffusion around the trenches located at the device periphery.

Three-dimensional simulation of an isolation trench refill process

We use EVOLVE-3D to simulate film profile evolution during an isolation trench refill process, focusing on the corner regions of the trench. EVOLVE-3D is a first principles, physically based simulator for low pressure deposition processes, i.e. the chemical reaction rate expressions used were developed from independent experiments. The trenches are refilled using two low pressure deposition processes: (1) low pressure chemical vapor deposition (LPCVD) of silicon dioxide from tetraethoxysilane (TEOS); (2) LPCVD of polysilicon (poly-Si) from silane. Three-dimensional deposition process simulations are used to estimate the film profiles after refilling in the idealized trenches with different aspect ratios. We find that the straight portions close before the trench corners close. If enough poly-Si is deposited to close the corners, the top of the void in the poly-Si moves up as a trench corner is approached. The position dependence of the void top should be considered in the optimization of the trench process, in order to avoid reopening trench corners when the poly-Si is etched back.