Transmission Line Pulse Testing Research Articles

Exploration of a Novel Electric-Fuse Device with a Simple Structure of Ni Metal on a SiO2 Dielectric for Electrostatic Discharge Protection under a Human Body Model.

On-chip electrostatic discharge (ESD) protection poses a challenge in the chip fabrication process. In this study, a novel electric fuse (E-fuse) device featuring a simple structure of Ni metal on a SiO2 dielectric for ESD protection was proposed, and the physical mechanism of its operation was investigated in detail. Experimental evaluations, utilizing transmission line pulse (TLP) testing and fusing performance analyses, reveal that the E-fuse, constructed with a Ni metal layer measuring 5 μm in width, 100 μm in length, and 5 nm in thickness, achieved a significant ESD protection voltage of 251 V (VHBM) and demonstrates low-voltage fusing at a bias voltage of 7 V. Compared to traditional ESD protection devices, the E-fuse boasts a smaller size and removability. To assess fusing performance, devices of varying sizes were tested using a fusing lifetime model. This study supports both theoretical and empirical evidence, enabling the adoption of cost-effective, straightforward E-fuse devices for ESD protection.

Characteristic parameter model and circuit‐level simulation of gate‐controlled dual direction SCR for on‐chip ESD protection

SummaryDual‐directional SCR (DDSCR) with bidirectional discharge paths and high robustness is widely employed for electrostatic discharge (ESD) protection in integrated circuits. However, the design and simulation of on‐chip ESD protection circuits for dual‐directional paths remain challenging due to a lack of relevant device models. This paper designs a Gate‐Controlled Dual‐Direction SCR (GDDSCR) for providing electrostatic discharge (ESD) protection in industry‐level temperature sensors. Furthermore, a new behavioral model is developed based on the GDDSCR for simulating ESD protection circuits along both forward and reverse paths. Experimental results demonstrate that the GDDSCR behavioral model accurately reproduces the IV characteristics observed in bidirectional transmission line pulse (TLP) tests. In addition, the equivalent circuit based on human body model (HBM) is used for transient simulation, and the accuracy of the model is verified by relevant HBM experiments. The proposed model allows the direct extraction of parameters such as trigger voltage (Vt1), holding voltage (Vh), and on‐state resistance (Ron) through TLP testing, facilitating easy application to other types of DDSCR devices.

Principle and verification of behavior model of gate-controlled SCR with adjustable on-resistance

This paper delineates the implementation of a gate-controlled Silicon Controlled Rectifier (SCR) behavioral model using Cadence software. The model is designed to tackle the absence of gate-control effect characteristics in extant models. This enables more precise simulation of the snapback behavior of such gate-controlled SCR devices under electrostatic discharge (ESD) stress. This work fabricates three types of SCR devices: Traditional SCR(T-SCR), Single-Gate SCR (SG-SCR), and a Double-Gate SCR (DG-SCR). These devices are fabricated using the 0.18 μm CMOS process and varied in the number of gates. The physical principles of the device are validated through two-dimensional electrical simulations. Furthermore, the model results are confirmed by the transmission line pulse (TLP) test results of the final device. The results demonstrate that the simulation results of the gate-controlled SCR behavioral model fit the TLP test results of the three SCR devices. The model’s applicability across different number of fingers devices confirms its scalability. Further, the model was simulated with the HBM equivalent circuit, and the comparison with the actual results confirmed the model’s applicability to HBM simulation.

Resistor-less power-rail ESD clamp circuit design with adjustable NMOS gate biased voltage

Based on the 0.18 μm CMOS process, proposed a new power-rail electrostatic discharge clamp circuit. The proposed circuit can adjust the voltage biased to the big clamp NMOS (Mbig) gate by adjusting the width of one MOS transistor, and the feedback path is designed to prolong the response time of Mbig. The simulation results demonstrated that the voltage biased to the Mbig of the proposed circuit has a relatively steady state and the Mbig has a longer response time, which can effectively reduce the damage to the gate oxide layer of the Mbig with large voltage overshoot. The transmission line pulse test results show that compared to the Mbig of the conventional circuit, the Mbig of the proposed circuit has higher trigger voltage, lower on-resistance, and better robustness.

A novel robust SCR with high holding voltage for on-chip ESD protection of industry-level bus

In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip.

Gate-controlled silicon controlled rectifier with adjustable clamping voltage using a photoelectric mechanism.

In order to flexibly control the voltage-clamping capability of silicon controlled rectifiers (SCRs), this paper proposes a photoelectric gate-controlled SCR (PGCSCR). Equivalent circuits and technology computer aided design (TCAD) simulations are used to analyze how the device works. The device has been validated by a standard 0.18 µm Bipolar CMOS DMOS (BCD) process. The ES620-50 Transmission Line Pulse (TLP) test system was used to verify the impact of the photoelectric effect on the electro-static discharge (ESD) characteristics of the device. The test result shows that the clamping voltage at the holding point of the PGCSCR under the light-free condition is 4.308 V. When the optical power is 5 W/µm2 and the 450 nm wavelength spot is irradiated on the surface of the device, the clamping voltage at the holding point of the PGCSCR is reduced to 3.655 V. And by changing the wavelength of the incident light spot (600 nm), the clamping voltage (3.409 V) of the device changes. Finally, based on the avalanche multiplication effect and the photoelectric effect, the change in the clamping voltage of the device can be further explained. PGCSCR can flexibly adjust the clamping voltage of the device according to the ESD window requirements of the target chip without changing the structure and size, and is expected to be applied in the fields of integrated optical circuits, opto-coupling, and optical communication.

Design of compact-diode-SCR with low-trigger voltage for full-chip ESD protection

In this article, a compact-diode-silicon-controlled rectifier (CDSCR) for full-chip electrostatic discharge (ESD) protection is proposed and verified in 0.18 μm Silicon-on-Insulator (SOI) Bipolar-CMOS-DMOS (BCD) process. Intrinsic parasitic SCRs and diodes are employed as the main ESD paths, which greatly reduces area consumption. Besides, due to the RC- triggered circuit, low trigger voltage and short turn-on time are realized. With equivalent circuit and two-dimensional (2D) technology computer-aided design (TCAD) simulation, the operation principle and working mechanism are analyzed. In addition, transmission line pulse (TLP) and very fast TLP (VF-TLP) testing results show that the CDSCR could can endure human body model (HBM) pulse of 3420 V without latch-up issue and protect the chip effectively in charge device model (CDM) event. Furthermore, the proposed structure exhibits high current handing ability during ESD stress conditions and sufficiently low leakage current during normal circuit operating conditions. The CDSCR is conformed to provide full-chip ESD protection for 1.2 V application.

Investigation on holding voltage of asymmetric DDSCR with floating heavy doping in 0.18 μm CMOS process

In the ESD protection design work, the most effective way to improve the holding voltage of bidirectional silicon-controlled rectifier or SCR device is to increase the distance between the cathode and anode of it. However, for DDSCR devices with multi-finger layouts, increasing this distance will result in a decrease in failure current and require a larger layout area. In this work, five types of asymmetric dual direction silicon-controlled rectifier devices with different floating heavy doping combinations are designed based on the traditional ADDSCR structure. Meanwhile, the dimensions, number of fingers, metal layout and number of CONT holes of the five ADDSCR structures are strictly kept the same, aiming at studying the influence of different floating heavy doping combinations on the performance of SCR devices and find the optimal floating heavy doping combination. Their ESD performances are predicted and verified through the two-dimensional device simulations and transmission line pulse (TLP) test results. All the five types of ADDSCR structures are designed to improve the holding voltage. From the results, the forward and reverse holding voltage of ADDSCR_PP, which is inserted floating P+ in NW and PW, are increased to 20.4 V and 17.6 V respectively, compared with the traditional devices without floating heavy doping at 14.2 V and 8.7 V. At the same time, the physical mechanism for the effect of floating heavy doping insert into NW and PW separately were investigated. Finally, the one that best meets the ESD window of automotive application is found.

Research on Turn-On Characteristics of New Light-Triggered Silicon Controlled Rectifier for Dual-Directional Electrostatic Discharge Protection

Dual-direction silicon-controlled rectifiers (DDSCRs) have been generally applied for bidirectional electrostatic discharge (ESD) protection due to their excellent robustness. However, the traditional DDSCR has a longer discharge path, which makes its turn-on speed relatively slow. In view of this problem, this paper proposes a light-triggered SCR (LTSCR). The device uses the depletion region of the DN-Well/P-Well to absorb photons and generate photogenerated carriers to facilitate the formation of SCR loop. Under the action of light triggering, the LTSCR can form a low-resistance SCR loop faster and effectively discharge the ESD pulse. Using the forward equivalent circuit model, the current relationships within the LTSCR device are analyzed. Furthermore, the working mechanism of the LTSCR is clearly described by Silvaco 2D device simulation and verified in transmission line pulse (TLP) test. Experimental results show that the LTSCR takes 7 ns less time to turn on under light compared to the dark environment. This light trigger method does not require special masks or any process modification during the fabrication process, and has wide adaptability.

A Novel DTSCR With Embedded MOS and Island Diodes for ESD Protection of High-Speed ICs

A novel diode-triggered silicon-controlled rectifier with embedded MOS and island diodes (DTSCR-EMOS-ID) is proposed and investigated. The DTSCR-EMOS-ID was fabricated in 0.18-μm and 22-nm CMOS processes for verifying the process transplantation. The fabricated DTSCR-EMOS-ID presents a low trigger voltage of 1.3 V, a small turn-on resistance of 8 mΩ/μm and a small parasitic capacitance of 43 fF. Meanwhile, the effective failure current and response time of DTSCR-EMOS-ID are optimized to 4.3 A and 3.6 ns, respectively. The DTSCR-EMOS-ID shows much better ESD performance than the conventional LVTSCR and DTSCR fabricated in the same process, which can be attributed to the diode triggering, gate coupling and large injection effects. Moreover, the TCAD simulation results of DTSCR-EMOS-ID agree well with the transmission line pulse testing results, further confirming that the proposed DTSCR-EMOS-ID can be widely used as an effective ESD protection device for high-speed ICs, without the limitation of the fabrication process.

Design of high voltage electrostatic protection device for CAN bus

The Dual-Direction Silicon Controlled Rectifier (DDSCR) device has dual-direction electrostatic protection function and strong current discharging ability, which is widely used in ESD on-chip protection. In this paper, a high performance symmetric high voltage Dual-Direction Silicon Controlled Rectifier with floating P+ (HVDDSCR_FP+) is designed for CAN bus under 0.18 μm BCD process. In order to predict and verify the ESD performance of the device, TCAD two-dimensional device simulation and Transmission Line Pulse (TLP) test system were used. The experimental results show that the HVDDSCR_FP + structure has not only symmetrical positive and reverse I-V curves, but also the characteristics of high holding voltage and high failure current. Compared with the traditional HVDDSCR, HVDDSCR_FP+, at 25V forward and reverse trigger voltages (Vt), has increased its holding voltage (Vh) from 12V to 20V, failure current (It2) from 5A to 35A. In the actual tape-out process, it is found that the width of the N-well has a great influence on the performance of the device. After analyzing the reason and improving it, the leakage current of the device is reduced from μA level to nA level.

Evaluation of stability and robustness of poly-Si resistors with different dopant concentrations

The stability and robustness of lightly and highly doped poly-Si resistors were evaluated. These resistors exhibited distinct electrical resistance properties and temperature dependences, which can be explained through the grain and grain boundary conduction mechanisms. The resistance shift saturated under the low current stress condition, but continued to increase under the high current stress condition. A novel carrier trapping density model was proposed to explain this behavior. A generalized free energy model that considered stress temperature and stress current dependences was proposed to account for the stability lifetime of a poly-Si resistor based on the resistance shift criterion. Robustness evaluation with transmission line pulse test revealed that the breakdown current exhibited a pulse width dependence which was further explained by a thermal-conduction energy model.

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

Robust Silicon-Controlled Rectifier With High-Holding Voltage for On-Chip Electrostatic Protection

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {t2}}{)}$ </tex-math></inline-formula> of 1.59 A at a finger width of 50 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation.

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

The holding voltage of electrostatic discharge (ESD) protecting structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters lead the protecting device to suffer latch-up risk at high ambient temperature. In this paper, the holding characteristics of the ESD protecting device at various ambient temperatures ranging from 30 ℃ to 195 ℃ are studied. The investigated ESD structure is the N-channel metal oxide semiconductor (NMOS) transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator process. The ESD characteristics of the device are measured by the transmission line pulse test system at different ambient temperatures. The test results show that the holding voltage (&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt;) decreases with temperature increasing. The TCAD simulation is carried out to support and analyze the experimental results, and the same trend of &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt; versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt; and holding current (&lt;i&gt;I&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt;) are discussed in detail. When the drain is subjected to the same current pulsing and the Source and Body are both grounded, the distributions of current density, electric potential, and injected electron density of NMOS at various temperatures are extracted and analyzed. When the Drain, Source, and Body are all grounded, the distributions of the electrostatic field at various temperatures are extracted and analyzed. The distribution of electric potential in NMOS indicates that the voltage drop on the Drain-Body junction (&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;DB&lt;/sub&gt;) is affected by ambient temperature significantly, and the variation of &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;DB&lt;/sub&gt; dominates the variation trend of &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt; with temperature increasing. The reducing electrostatic field and increasing injected electron density with temperature decreasing contribute to the decreasing of &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;DB&lt;/sub&gt;. The trend of &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt; and parasitic Body resistance (&lt;i&gt;R&lt;/i&gt;&lt;sub&gt;Body&lt;/sub&gt;) weakens the temperature dependence of the &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt;. The current gain of parasitic bipolar transistor (&lt;i&gt;β&lt;/i&gt;) decreases with ambient temperature rising, which is the main contributor to the decreasing of &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt;. Therefore, increasing &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;H&lt;/sub&gt; and &lt;i&gt;R&lt;/i&gt;&lt;sub&gt;Body&lt;/sub&gt; is helpful in reducing the temperature dependence of the latch-immune ESD protection structure.

A novel percolation model of leakage fluctuation behavior in gate-control dual-direction silicon controlled rectifier

Gate structures are used as efficient auxiliary components to improve the electrostatic discharge (ESD) performance of traditional silicon controlled rectifiers (SCRs). However, it has not been explored how the gate geometry potentially affects leakage behaviors and ESD characteristics of SCR devices. In this paper, a novel percolation model is proposed to address this problem. The percolation model fundamentally interprets the leakage fluctuation behavior of the gate-control dual-direction silicon controlled rectifier (GC-DDSCR) under ESD events. Two key parameters breakdown charge (QBD) and tunneling current (Jg) are simulated to link the gate geometry and gate oxide quality, revealing the principle of the leakage fluctuation behavior. The leakage fluctuation behavior may cause GC-DDSCR to work in an unstable state, leading to the premature functional failure of the intrinsic SCR path. Two GC-DDSCRs with different gate sizes are fabricated under a 0.5 μm CMOS technology and characterized by a transmission line pulse (TLP) test. Experiment results show the GC-DDSCR with a larger gate size is more prone to the leakage fluctuation behavior and the premature functional failure. The percolation model is qualitatively verified and the understanding of the gate structure in ESD devices is deepened.

Study on the high-temperature triggering and holding characteristics of PDSOI SCR devices

In this paper, the triggering and holding characteristics of electrostatic discharge (ESD) protection devices operating under various ambient temperatures ranging from 25 °C to 300 °C are investigated. The measured ESD protection devices were silicon-controlled rectifier (SCR) devices fabricated in 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. Measurements were conducted using the transmission line pulse (TLP) test system. The triggering voltage, VT1, and the holding voltage, VH, of the SCR devices show negative coefficient phenomenon with the increasing temperature. The similarities and differences between the triggering condition and the holding condition are analyzed in detail. The underlying physical mechanisms related to the effects of temperature on the VT1 and VH are provided by the assist of technology computer-aided design (TCAD) simulation.

Analyzing the impact of guard-ring on different dual-direction SCR by device simulation and TLP measurement

In this paper, the impact of the traditional interdigital DDSCR structure (TI-DDSCR) and the embedded DDSCR (EM-DDSCR) structure with and without P+ guard-ring is analyzed under the 0.5-μm complementary and double-diffused MOSFET (CDMOS) technology. In order to verify and predict the characteristics of those electrostatic discharge (ESD) protection devices, a transmission line pulse (TLP) testing system and device simulation platform have been used in this work. The test results show that the introduction of P + guard ring will increase the device forward trigger voltage (Vt1) by about 3 V and forward holding voltage (Vh) by 4-6 V, but has little effect on the forward failure current (It2). The reverse Vh is reduced by 4–6 V, while the reverse It2 depends on the layout geometry. Due to the different layout geometry, on the TI-DDSCR structure with P+ guard ring, their reverse It2 is reduced from 13.07A to 8.05A. On the contrary, on the EM-DDSCR with P+ guard ring, their reverse It2 increased from 6.55A to 10.10A.

An on-chip TVS design to meet system level ESD protection for RS485 transceiver

RS485 interface is widely used in the area of industrial control and remote meter reading, which are often subjected to serious electrostatic damage. A new On-Chip TVS (OCT) structure without extra process modification and a novel electrostatic discharge method for RS485 transceiver IC have been proposed. It is composed of a serie of Zener diodes and fabricated in 5V/18V/24V 0.5µm CDMOS technology. A 100ns pulse width of the Transmission Line Pulsing (TLP) test is performed for this proposed OCT. The driver circuit itself can work as an ESD device as well. The OCT trigger voltage is compatible with the signal level of RS485 standard. The OCT device protection level of human-body-model (HBM) is up to 16.34kV. RS485 transceiver integrated with OCT has also been tested in order to verify its reliability. The results indicate that it can pass the IEC61000-4-2 contact ±10kV stress and IEC 61000−4−4 Electrical Fast Transient (EFT) ±2.2kV without any hard damages and latch-up issues. The RS485 transceiver integrated with the OCT allows error-free data rate transfer up to 500 kbps. The chip occupies a silicon area of 2.4×1.17mm2.